ARM Macro Assembler Page 1 1 00000000 ; ARM remote emulator and monitor programme 2 00000000 ; J. Garside - University of Manchester - March 2003 3 00000000 ; 4 00000000 ; TO DO: 5 00000000 ; 6 00000000 ; EMULATOR 7 00000000 ; 8 00000000 ; Detailed undefined trapping (need reduced since V.5) 9 00000000 ; Thumb stuff (could make (ROM) look-up table for most?) 10 00000000 ; 11 00000000 ; Consider storing PC+8 in register bank for reads 12 00000000 ; 13 00000000 ; Wrap up memory transfers to allow trap checking 14 00000000 ; (Return {okay, abort, watchpoint}?) 15 00000000 ; Watchpoints & Register trap points 16 00000000 ; Aborts (enableable) 17 00000000 ; 18 00000000 ; Lose "tube_too" @@@ 19 00000000 ; 20 00000000 ; 21 00000000 ; MONITOR 22 00000000 ; 23 00000000 ; Virtex bus speed changer @@@ Done?? 24 00000000 ; Revise & expand command set 25 00000000 ; copy 26 00000000 ; find 27 00000000 ; Separate breakpoint enable command (+ other flags) 28 00000000 ; Return version number (& boot version number?) command 29 00000000 ; 30 00000000 ; GENERAL 31 00000000 ; 32 00000000 ; Finish sorting out I/O map (Virtex, ++) & proper memor y handling 33 00000000 ; (eventually) make proper interrupt driven scheduler 34 00000000 ; 35 00000000 ; Lots of testing :-] 36 00000000 37 00000000 38 00000000 ; General register usage 39 00000000 ; R7 points at shared variables 40 00000000 ; R8 is flags for run options (emulator) 41 00000000 ; R9 points at register definitions 42 00000000 ; R10 is current instruction (emulator) 43 00000000 ; R11 is PC (emulator) (leave in reg. set ? @@@) 44 00000000 ; R12 is CPSR (emulator) 45 00000000 46 00000000 47 00000000 00000001 Maker EQU 1 48 00000000 00000002 Version EQU 2 49 00000000 0000000A day EQU 10 50 00000000 00000003 month EQU 03 51 00000000 00000003 year EQU 03 ARM Macro Assembler Page 2 52 00000000 53 00000000 GBLL Virtex_E 54 00000000 TRUE Virtex_E SETL {TRUE} 55 00000000 56 00000000 GET header.s ; Register definitions etc. 1 00000000 ;------------------------------------------------------- ----------------------- 2 00000000 ; Headers and definitions for AT91 basic set up. 3 00000000 ; Last modified 10/1/03 4 00000000 5 00000000 ; General ARM headers 6 00000000 7 00000000 D SP RN R13 ; Register synonyms 8 00000000 E LR RN R14 9 00000000 F PC RN R15 10 00000000 11 00000000 8 H0 RN R8 ; Thumb register synonyms 12 00000000 9 H1 RN R9 13 00000000 A H2 RN R10 14 00000000 B H3 RN R11 15 00000000 C H4 RN R12 16 00000000 D H5 RN R13 17 00000000 E H6 RN R14 18 00000000 F H7 RN R15 19 00000000 20 00000000 00000080 I_bit EQU &00000080 ; Interrupt disable bit in s tatus word 21 00000000 00000040 F_bit EQU &00000040 ; FIQ disable bit in status word 22 00000000 00000020 T_bit EQU &00000020 ; Thumb bit mask in status w ord 23 00000000 24 00000000 FFFFFFFF TRUE EQU -1 25 00000000 00000000 FALSE EQU 0 26 00000000 27 00000000 0000000F Mode_bits EQU &F ; Bits considered as operati ng mode 28 00000000 00000000 User_mode ARM Macro Assembler Page 3 EQU &0 29 00000000 00000001 FIQ_mode EQU &1 30 00000000 00000002 IRQ_mode EQU &2 31 00000000 00000003 Supervisor_mode EQU &3 32 00000000 00000007 Abort_mode EQU &7 33 00000000 0000000B Undefined_mode EQU &B 34 00000000 0000000F System_mode EQU &F 35 00000000 36 00000000 00000010 mode32 EQU &10 37 00000000 38 00000000 ;------------------------------------------------------- ----------------------- 39 00000000 40 00000000 00000004 cEOT EQU 4 ; Basic ASCII characters 41 00000000 0000000A cLF EQU 10 42 00000000 0000000C cFF EQU 12 43 00000000 0000000D cCR EQU 13 44 00000000 45 00000000 00000000 ttr EQU 0 ; String terminator 46 00000000 47 00000000 FF000000 byte3 EQU &FF000000 ; Byte masks 48 00000000 00FF0000 byte2 EQU &00FF0000 49 00000000 0000FF00 byte1 EQU &0000FF00 50 00000000 000000FF byte0 EQU &000000FF 51 00000000 52 00000000 ;------------------------------------------------------- ----------------------- 53 00000000 ; Specific header for AT91 board 54 00000000 55 00000000 00000000 FASTRAM_base EQU &00000000 ; Prescribed - run time addr ess 56 00000000 57 00000000 00080000 RAM_chip_size EQU &00080000 ; 512 Kbytes ARM Macro Assembler Page 4 58 00000000 59 00000000 08000000 ROM_base EQU &08000000 ; These are chosen by the us er 60 00000000 10000000 RAM_base EQU &10000000 61 00000000 20000000 VIRTEX_base EQU &20000000 62 00000000 30000000 ETHERNET_base EQU &30000000 63 00000000 40000000 SPARTAN_base EQU &40000000 64 00000000 65 00000000 66 00000000 ; Flags passed to application 67 00000000 00000001 LCD_present_flag EQU &00000001 ; If LCD detected 68 00000000 00000100 Power_up_flag EQU &00000100 ; If power-up reset 69 00000000 00000200 Watchdogged_flag EQU &00000200 ; If watchdog reset 70 00000000 71 00000000 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 72 00000000 73 00000000 00003FFC Serial_number_addr EQU &3FFC ; 74 00000000 75 00000000 00004000 boot_table_address EQU &4000 ; 16Kbytes up to clear botto m block 76 00000000 ; Boot programme MUST be shorter 77 00000000 00000008 boot_table_shifts EQU 8 ; Log of boot table length ( &100) 78 00000000 00000100 boot_table_entry_length EQU 1 :SHL: boot_table_shifts 79 00000000 ; Can't define this the other way :-( 80 00000000 81 00000000 ; Boot block offsets (don't really belong here) 82 00000000 83 00000000 00000004 Btab_flags EQU &04 84 00000000 00000008 Btab_RAM_start EQU &08 ARM Macro Assembler Page 5 85 00000000 0000000C Btab_RAM_length EQU &0C 86 00000000 00000010 Btab_ROM_start EQU &10 87 00000000 00000014 Btab_ROM_length EQU &14 88 00000000 00000018 Btab_exec_offset EQU &18 89 00000000 0000001C Btab_exec_CPSR EQU &1C 90 00000000 00000020 Btab_spartan_data EQU &20 91 00000000 00000024 Btab_spartan_length EQU &24 92 00000000 00000028 Btab_virtex_data EQU &28 93 00000000 0000002C Btab_virtex_length EQU &2C 94 00000000 00000030 Btab_LCD_message EQU &30 95 00000000 96 00000000 ; Boot flag definitions 97 00000000 00000001 BtFlg_LCD_message EQU &00000001 98 00000000 00000002 BtFlg_LCD_light EQU &00000002 99 00000000 00000004 BtFlg_LED_on EQU &00000004 100 00000000 00000008 BtFlg_RAM_boot EQU &00000008 ; TBC 101 00000000 00000010 BtFlg_ROM_check EQU &00000010 102 00000000 00000100 BtFlg_RAM_clr_int EQU &00000100 103 00000000 00000200 BtFlg_RAM_clr_ext EQU &00000200 104 00000000 105 00000000 ; FPGA block offsets (don't really belong here either) 106 00000000 107 00000000 00000004 FPGA_offset EQU 4 ARM Macro Assembler Page 6 108 00000000 00000008 FPGA_length EQU 8 109 00000000 110 00000000 111 00000000 ; Default stack sizes (user gets remainder) 112 00000000 113 00000000 00000200 Supervisor_stack EQU &200 114 00000000 00000080 FIQ_stack EQU &80 115 00000000 00000080 IRQ_stack EQU &80 116 00000000 00000080 Abort_stack EQU &80 117 00000000 00000080 Undefined_stack EQU &80 118 00000000 119 00000000 ;------------------------------------------------------- ----------------------- 120 00000000 ; AT91 on-board register definitions 121 00000000 122 00000000 FFFFFFFF DEV_TERMINATE EQU -1 ; Not a peripheral address 123 00000000 ; used to terminate set-up tables 124 00000000 125 00000000 126 00000000 ; External bus interface register addresses 127 00000000 128 00000000 FFE00000 EBI_base EQU &FFE00000 129 00000000 130 00000000 00000000 EBI_CSR0 EQU &00 131 00000000 00000004 EBI_CSR1 EQU &04 132 00000000 00000008 EBI_CSR2 EQU &08 133 00000000 0000000C EBI_CSR3 EQU &0C 134 00000000 00000010 EBI_CSR4 EQU &10 135 00000000 00000014 EBI_CSR5 EQU &14 136 00000000 00000018 EBI_CSR6 ARM Macro Assembler Page 7 EQU &18 137 00000000 0000001C EBI_CSR7 EQU &1C 138 00000000 00000020 EBI_RCR EQU &20 139 00000000 00000024 EBI_MCR EQU &24 140 00000000 141 00000000 ; EBI CSR bit fields 142 00000000 00002000 CSEN EQU &00002000 ; Chip select enable 143 00000000 00001000 BAT EQU &00001000 ; Byte access type (byte sel ect) 144 00000000 00000200 TDF1 EQU &00000200 ; One data float cycle 145 00000000 00000400 TDF2 EQU &00000400 ; Two data float cycles 146 00000000 00000600 TDF3 EQU &00000600 ; Three data float cycles 147 00000000 00000800 TDF4 EQU &00000800 ; Four data float cycles 148 00000000 00000A00 TDF5 EQU &00000A00 ; Five data float cycles 149 00000000 00000C00 TDF6 EQU &00000C00 ; Six data float cycles 150 00000000 00000E00 TDF7 EQU &00000E00 ; Seven data float cycles 151 00000000 00000000 Pg1M EQU &00000000 ; 1 Mbyte pages 152 00000000 00000080 Pg4M EQU &00000080 ; 4 Mbyte pages 153 00000000 00000100 Pg16M EQU &00000100 ; 16 Mbyte pages 154 00000000 00000180 Pg64M EQU &00000180 ; 64 Mbyte pages 155 00000000 00000020 NWS1 EQU &00000020 ; 1 wait state (WSE included ) 156 00000000 00000024 NWS2 EQU &00000024 ; 2 wait states 157 00000000 00000028 NWS3 EQU &00000028 ; 3 wait states 158 00000000 0000002C NWS4 EQU &0000002C ; 4 wait states 159 00000000 00000030 NWS5 EQU &00000030 ; 5 wait states 160 00000000 00000034 NWS6 EQU &00000034 ; 6 wait states 161 00000000 00000038 NWS7 EQU &00000038 ; 7 wait states 162 00000000 0000003C NWS8 EQU &0000003C ; 8 wait states 163 00000000 00000002 DBW8 EQU &00000002 ; 8-bit bus 164 00000000 00000001 DBW16 EQU &00000001 ; 16-bit bus 165 00000000 ARM Macro Assembler Page 8 166 00000000 ; "Special function" register addresses 167 00000000 168 00000000 FFF00000 SF_base EQU &FFF00000 169 00000000 170 00000000 00000000 SF_CIDR EQU &00 171 00000000 00000004 SF_EXID EQU &04 172 00000000 00000008 SF_RSR EQU &08 173 00000000 0000000C SF_MMR EQU &0C 174 00000000 00000018 SF_PMR EQU &18 175 00000000 176 00000000 177 00000000 ; PIO register addresses 178 00000000 179 00000000 FFFF0000 PIO_base EQU &FFFF0000 180 00000000 181 00000000 00000000 PIO_PER EQU &00 182 00000000 00000004 PIO_PDR EQU &04 183 00000000 00000008 PIO_PSR EQU &08 184 00000000 00000010 PIO_OER EQU &10 185 00000000 00000014 PIO_ODR EQU &14 186 00000000 00000018 PIO_OSR EQU &18 187 00000000 00000020 PIO_IFER EQU &20 188 00000000 00000024 PIO_IFDR EQU &24 189 00000000 00000028 PIO_IFSR EQU &28 190 00000000 00000030 PIO_SODR EQU &30 191 00000000 00000034 PIO_CODR EQU &34 192 00000000 00000038 PIO_ODSR EQU &38 193 00000000 0000003C PIO_PDSR EQU &3C 194 00000000 00000040 PIO_IER EQU &40 195 00000000 00000044 ARM Macro Assembler Page 9 PIO_IDR EQU &44 196 00000000 00000048 PIO_IMR EQU &48 197 00000000 0000004C PIO_ISR EQU &4C 198 00000000 199 00000000 200 00000000 ; Power saving register addresses 201 00000000 202 00000000 FFFF4000 PS_base EQU &FFFF4000 203 00000000 204 00000000 00000000 PS_CR EQU &00 205 00000000 00000004 PS_PCER EQU &04 206 00000000 00000008 PS_PCDR EQU &08 207 00000000 0000000C PS_PCSR EQU &0C 208 00000000 209 00000000 210 00000000 ; Watchdog register addresses 211 00000000 212 00000000 FFFF8000 WD_base EQU &FFFF8000 213 00000000 214 00000000 00000000 WD_OMR EQU &00 215 00000000 00000004 WD_CMR EQU &04 216 00000000 00000008 WD_CR EQU &08 217 00000000 0000000C WD_SR EQU &0C 218 00000000 219 00000000 220 00000000 ; USART[0:1] register addresses 221 00000000 222 00000000 FFFD0000 US0_base EQU &FFFD0000 ; Serial port 0 223 00000000 FFFCC000 US1_base EQU &FFFCC000 ; Serial port 1 224 00000000 225 00000000 00000000 US_CR EQU &00 226 00000000 00000004 US_MR EQU &04 227 00000000 00000008 US_IER EQU &08 228 00000000 0000000C US_IDR EQU &0C 229 00000000 00000010 US_IMR EQU &10 230 00000000 00000014 US_CSR EQU &14 231 00000000 00000018 ARM Macro Assembler Page 10 US_RHR EQU &18 232 00000000 0000001C US_THR EQU &1C 233 00000000 00000020 US_BRGR EQU &20 234 00000000 00000024 US_RTOR EQU &24 235 00000000 00000028 US_TTGR EQU &28 236 00000000 00000030 US_RPR EQU &30 237 00000000 00000034 US_RCR EQU &34 238 00000000 00000038 US_TPR EQU &38 239 00000000 0000003C US_TCR EQU &3C 240 00000000 241 00000000 ; USART bit definitions 242 00000000 243 00000000 00000001 RxRdy EQU &001 ; Channel Status Register bi ts 244 00000000 00000002 TxRdy EQU &002 245 00000000 00000004 RxBrk EQU &004 246 00000000 00000008 EndRx EQU &008 247 00000000 00000010 EndTx EQU &010 248 00000000 00000020 OvrE EQU &020 249 00000000 00000040 FramE EQU &040 250 00000000 00000080 ParE EQU &080 251 00000000 00000100 Timeout EQU &100 252 00000000 00000200 TxEmpty EQU &200 253 00000000 254 00000000 255 00000000 ; Timer/Counter register addresses 256 00000000 257 00000000 FFFE0000 TC_base EQU &FFFE0000 258 00000000 259 00000000 00000000 TC_CHL0 EQU &00 ; Base offset for TC0 260 00000000 00000040 TC_CHL1 EQU &40 ; Base offset for TC1 261 00000000 00000080 TC_CHL2 EQU &80 ; Base offset for TC2 262 00000000 000000C0 TC_BCR EQU &C0 ; Block control register 263 00000000 000000C4 TC_BMR EQU &C4 ; Block mode register 264 00000000 ARM Macro Assembler Page 11 265 00000000 ; Register offsets within for TC 266 00000000 00000000 TC_CCR EQU &00 267 00000000 00000004 TC_CMR EQU &04 268 00000000 00000010 TC_CVR EQU &10 269 00000000 00000014 TC_RA EQU &14 270 00000000 00000018 TC_RB EQU &18 271 00000000 0000001C TC_RC EQU &1C 272 00000000 00000020 TC_SR EQU &20 273 00000000 00000024 TC_IER EQU &24 274 00000000 00000028 TC_IDR EQU &28 275 00000000 0000002C TC_IMR EQU &2C 276 00000000 277 00000000 278 00000000 ; Interrupt controller register addresses 279 00000000 280 00000000 FFFFF000 AIC_base EQU &FFFFF000 281 00000000 282 00000000 00000000 AIC_SMR0 EQU &00 ; Source mode/priority - FIQ 283 00000000 00000004 AIC_SMR1 EQU &04 ; Source mode/priority - Sof tware 284 00000000 00000008 AIC_SMR2 EQU &08 ; Source mode/priority - USA RT #0 285 00000000 0000000C AIC_SMR3 EQU &0C ; Source mode/priority - USA RT #1 286 00000000 00000010 AIC_SMR4 EQU &10 ; Source mode/priority - Tim er #0 287 00000000 00000014 AIC_SMR5 EQU &14 ; Source mode/priority - Tim er #1 288 00000000 00000018 AIC_SMR6 EQU &18 ; Source mode/priority - Tim er #2 289 00000000 0000001C AIC_SMR7 ARM Macro Assembler Page 12 EQU &1C ; Source mode/priority - Wat chdog 290 00000000 00000020 AIC_SMR8 EQU &20 ; Source mode/priority - PIO 291 00000000 00000040 AIC_SMR16 EQU &40 ; Source mode/priority - IRQ #0 (Spartan) 292 00000000 00000044 AIC_SMR17 EQU &44 ; Source mode/priority - IRQ #1 (Virtex) 293 00000000 00000048 AIC_SMR18 EQU &48 ; Source mode/priority - IRQ #2 (Ethernet) 294 00000000 295 00000000 00000080 AIC_SVR0 EQU &80 ; Source vector - FIQ 296 00000000 00000084 AIC_SVR1 EQU &84 ; Source vector - Software 297 00000000 00000088 AIC_SVR2 EQU &88 ; Source vector - USART #0 298 00000000 0000008C AIC_SVR3 EQU &8C ; Source vector - USART #1 299 00000000 00000090 AIC_SVR4 EQU &90 ; Source vector - Timer #0 300 00000000 00000094 AIC_SVR5 EQU &94 ; Source vector - Timer #1 301 00000000 00000098 AIC_SVR6 EQU &98 ; Source vector - Timer #2 302 00000000 0000009C AIC_SVR7 EQU &9C ; Source vector - Watchdog 303 00000000 000000A0 AIC_SVR8 EQU &A0 ; Source vector - PIO 304 00000000 000000C0 AIC_SVR16 EQU &C0 ; Source vector - IRQ #0 (Sp artan) 305 00000000 000000C4 AIC_SVR17 EQU &C4 ; Source vector - IRQ #1 (Vi rtex) 306 00000000 000000C8 AIC_SVR18 EQU &C8 ; Source vector - IRQ #2 (Et hernet) 307 00000000 ARM Macro Assembler Page 13 308 00000000 00000100 AIC_IVR EQU &100 ; Vector register (IRQ) 309 00000000 00000104 AIC_FVR EQU &104 ; Vector register (FIQ) 310 00000000 00000108 AIC_ISR EQU &108 ; Interrupt status 311 00000000 0000010C AIC_IPR EQU &10C ; (Potential) interrupts pen ding 312 00000000 00000110 AIC_IMR EQU &110 ; Interrupt mask 313 00000000 00000114 AIC_CISR EQU &114 ; Core IRQ/FIQ status 314 00000000 00000120 AIC_IECR EQU &120 ; Interrupt enable 315 00000000 00000124 AIC_IDCR EQU &124 ; Interrupt disable 316 00000000 00000128 AIC_ICCR EQU &128 ; Interrupt clear 317 00000000 0000012C AIC_ISCR EQU &12C ; Interrupt set 318 00000000 00000130 AIC_EOICR EQU &130 ; Signal end of interrupt 319 00000000 00000134 AIC_SPU EQU &134 ; Spurious interrupt vector 320 00000000 321 00000000 ;------------------------------------------------------- ----------------------- 322 00000000 ; `Magic' numbers used to derive baud rate divider from clock speed 323 00000000 324 00000000 0001D7DC baud115k2 EQU &0001D7DC ; 0.1152 * &10000 * 16 325 00000000 00009D49 baud38k4 EQU &00009D49 ; 0.0384 * &10000 * 16 326 00000000 00004EA5 baud19k2 EQU &00004EA5 ; 0.0192 * &10000 * 16 327 00000000 00002752 baud9600 EQU &00002752 ; 0.0096 * &10000 * 16 328 00000000 329 00000000 ;------------------------------------------------------- ----------------------- 330 00000000 ; Local PIO bit definitions for AT91 board 331 00000000 332 00000000 00000200 AT91_Spartan_IRQ EQU &00000200 ; 333 00000000 00000400 AT91_Virtex_IRQ ARM Macro Assembler Page 14 EQU &00000400 ; 334 00000000 00000800 AT91_Ether_IRQ EQU &00000800 ; 335 00000000 00001000 AT91_FIQ EQU &00001000 ; Open drain (Also HDC signa l) 336 00000000 337 00000000 00010000 AT91_Spartan_prog EQU &00010000 ; Active low 338 00000000 00020000 AT91_Virtex_prog EQU &00020000 ; Active low 339 00000000 00040000 AT91_Spartan_init EQU &00040000 ; Active low input 340 00000000 00080000 AT91_Virtex_init EQU &00080000 ; Active low input 341 00000000 342 00000000 00800000 AT91_Spartan_CS1 EQU &00800000 ; Also LCD_RS 343 00000000 00001000 AT91_Spartan_HDC EQU &00001000 ; Also FIQ signal 344 00000000 00002000 AT91_FPGA_baud EQU &00002000 ; Also DOUT - 345 00000000 ; driven low by Spartan at configuration time 346 00000000 347 00000000 00100000 AT91_LCD_light EQU &00100000 ; 348 00000000 349 00000000 00800000 AT91_LCD_RS EQU &00800000 ; Also Spartan CS1 350 00000000 01000000 AT91_LCD_En EQU &01000000 ; 351 00000000 02000000 AT91_LCD_RW EQU &02000000 ; 352 00000000 353 00000000 40000000 AT91_LED_En EQU &40000000 ; 354 00000000 355 00000000 00000080 AT91_LCD_busy EQU &00000080 ; MSB of data bus 356 00000000 357 00000000 ;------------------------------------------------------- ----------------------- 358 00000000 359 00000000 00000000 ARM Macro Assembler Page 15 prog_SA0_data EQU &0 ; XPIO register offsets 360 00000000 00000001 prog_SA0_ctrl EQU &1 361 00000000 00000002 prog_SA1_data EQU &2 362 00000000 00000003 prog_SA1_ctrl EQU &3 363 00000000 00000004 prog_SB0_data EQU &4 364 00000000 00000005 prog_SB0_ctrl EQU &5 365 00000000 00000006 prog_SB1_data EQU &6 366 00000000 00000007 prog_SB1_ctrl EQU &7 367 00000000 00000008 prog_VS0_data EQU &8 368 00000000 00000009 prog_VS0_ctrl EQU &9 369 00000000 0000000A prog_VS1_data EQU &A 370 00000000 0000000B prog_VS1_ctrl EQU &B 371 00000000 372 00000000 ;------------------------------------------------------- ----------------------- 373 00000000 END 57 00000000 GET link_addresses.s ; Addresses (etc.) of p rogrammes 1 00000000 ;------------------------------------------------------- ----------------------- 2 00000000 ; Hand-built table for linking programmes in AT91 boot_t able 3 00000000 ; Last modified 20/11/01 4 00000000 5 00000000 ; Items marked with ** are hand-linked and will need che cking if code expands 6 00000000 7 00000000 8 00000000 00000000 Start EQU 0 9 00000000 10 00000000 00001000 ROM_loader_image_position EQU &1000 ; ** Plenty of space above b oot code 11 00000000 00000500 ARM Macro Assembler Page 16 ROM_loader_image_length EQU &500 ; ** Overestimate 12 00000000 00000010 ROM_loader_branch_space EQU &10 ; I wish "ORIGIN" worked :-( 13 00000000 14 00000000 00010000 Mon_ROM EQU &10000 ; ** 15 00000000 00001000 Mon_RAM_image_position EQU &1000 ; ** 16 00000000 00000280 Mon_RAM_image_length EQU &280 ; ** 17 00000000 18 00000000 00020000 Flash_prog EQU &20000 ; ** 19 00000000 00030000 Angel_start EQU &30000 ; ** 20 00000000 21 00000000 00008000 XPIO_config EQU &8000 ; ** 22 00000000 23 00000000 ;------------------------------------------------------- ----------------------- 24 00000000 END 58 00000000 59 00000000 60 00000000 80000000 Nflag EQU &80000000 ; N flag 61 00000000 40000000 Zflag EQU &40000000 ; Z flag 62 00000000 20000000 Cflag EQU &20000000 ; C flag 63 00000000 10000000 Vflag EQU &10000000 ; V flag 64 00000000 65 00000000 01000000 Lbit EQU &01000000 ; Link bit in branches 66 00000000 00100000 Sbit EQU &00100000 ; Set flags bit 67 00000000 01000000 Pbit EQU &01000000 ; Pre-index bit 68 00000000 00800000 Ubit EQU &00800000 ; Up bit 69 00000000 00400000 Bbit EQU &00400000 ; Byte bit 70 00000000 00200000 Wbit EQU &00200000 ; Writeback bit 71 00000000 00400000 Rbit EQU &00400000 ; SPSR indicator 72 00000000 00100000 Ldbit EQU &00100000 ; Load bit 73 00000000 74 00000000 00200000 ARM Macro Assembler Page 17 MUL_A_bit EQU &00200000 ; Accumulate or don't 75 00000000 00400000 MUL_U_bit EQU &00400000 ; Signed or unsigned 76 00000000 00800000 MUL_L_bit EQU &00800000 ; Short or long 77 00000000 78 00000000 00400000 LSM_S_bit EQU &00400000 ; S bit set 79 00000000 00008000 LSM_PC_bit EQU &00008000 ; Mask for PC 80 00000000 81 00000000 82 00000000 10000000 IO_area_start EQU &10000000 ; Virtual address 83 00000000 20000000 IO_area_end EQU &20000000 ; Virtual address 84 00000000 85 00000000 03000000 tube EQU &03000000 ; Rationalise into I/O map 86 00000000 0000C000 tube_too EQU &0000C000 ; @@@ Infringes normal map! @@@ 87 00000000 88 00000000 00001000 nFIQ_wire EQU AT91_FIQ 89 00000000 ;nIRQ_wire EQU AT91_Spartan_init 90 00000000 91 00000000 92 00000000 00000020 Run_W_bit EQU &20 ; Bits in "run" command 93 00000000 00000010 Run_B_bit EQU &10 ; used to allow stepping 94 00000000 00000008 Run_M_bit EQU &08 ; through various routines 95 00000000 00000004 Run_S_bit EQU &04 ; 96 00000000 00000002 Run_P_bit EQU &02 ; 97 00000000 00000001 Run_BB_bit EQU &01 ; Extra breakpoint enable 98 00000000 99 00000000 00000200 Run_I_bit EQU &200 ; ARM Macro Assembler Page 18 100 00000000 00000100 Run_F_bit EQU &100 ; 101 00000000 102 00000000 103 00000000 104 00000000 ; These states are sorted on bits 7..6 into four categor ies 105 00000000 ; Do not alter without checking cross reference #A# 106 00000000 107 00000000 00000000 State_hard_reset EQU &00 ; Hardware reset 108 00000000 00000001 State_reset EQU &01 ; Soft reset performed 109 00000000 00000002 State_to_reset EQU &02 ; Soft reset requested 110 00000000 111 00000000 00000040 State_stopped EQU &40 ; Stopped by user while runn ing 112 00000000 00000041 State_stop_req EQU &41 ; Stopped by software reques t 113 00000000 00000042 State_stop_bkpt EQU &42 ; Stopped by breakpoint 114 00000000 00000043 State_count_out EQU &43 ; Stopped by stepping finish ing 115 00000000 116 00000000 00000080 State_running EQU &80 ; Running 117 00000000 00000081 State_running_BL EQU &81 ; Running procedure 118 00000000 00000082 State_running_SWI EQU &82 ; Running SWI 119 00000000 00000083 State_running_IRQ EQU &83 ; Running 120 00000000 00000084 State_running_FIQ EQU &84 ; Running 121 00000000 00000085 State_running_abt EQU &85 ; Running 122 00000000 123 00000000 000000C0 State_stepping EQU &C0 ; Stepping 124 00000000 ARM Macro Assembler Page 19 125 00000000 126 00000000 ; Internal interrupt bit definitions 127 00000000 00000001 Int_timer_compare EQU &01 ; Timer matches comparison r egister 128 00000000 00000002 Int_Spartan EQU &02 ; 129 00000000 00000004 Int_Virtex EQU &04 ; 130 00000000 00000008 Int_Ethernet EQU &08 ; 131 00000000 00000010 Int_Rx_ready EQU &10 ; Character received on seri al line 132 00000000 00000020 Int_Tx_ready EQU &20 ; Serial transmit buffer not full 133 00000000 00000040 Int_R_button EQU &40 ; 134 00000000 00000080 Int_L_button EQU &80 ; 135 00000000 136 00000000 00000001 UART_RxRdy EQU &01 ; UART status bits 137 00000000 00000002 UART_TxRdy EQU &02 ; 138 00000000 139 00000000 20000000 Spartan_page EQU &20000000 ; Emulator address of Sparta n 140 00000000 30000000 Virtex_page EQU &30000000 ; Emulator address of Virtex 141 00000000 142 00000000 00000008 breakpoint_max EQU 8 ; Number of breakpoints 143 00000000 00000001 watchpoint_max EQU 1 ; Number of watchpoints 144 00000000 145 00000000 00000002 Terminal_feature EQU 2 ; Feature number SEE "enq_me ssage" 146 00000000 00000010 Terminal_Rx_buff_length ARM Macro Assembler Page 20 EQU 16 ; Buffers for `terminal' fea ture 147 00000000 00000010 Terminal_Tx_buff_length EQU 16 ; 148 00000000 149 00000000 00000000 Reset_PC EQU &00000000 150 00000000 000000D3 Reset_CPSR EQU &000000D3 151 00000000 152 00000000 153 00000000 ; Stack lengths in words (with considerable margin) 154 00000000 00000028 Comm_stack_length EQU 40 155 00000000 00000028 Exec_stack_length EQU 40 ; 20 + 20 for Tube output de sched. 156 00000000 00000008 Int_stack_length EQU 8 157 00000000 158 00000000 159 00000000 ; Serial command definitions (some of them) 160 00000000 161 00000000 00000004 Com_reset EQU &04 162 00000000 00000020 Com_enq EQU &20 163 00000000 00000021 Com_stop EQU &21 164 00000000 165 00000000 166 00000000 AREA boot, CODE, READONLY 167 00000000 ENTRY 168 00000000 169 00000000 ;Mon_ROM 170 00000000 EA000071 B Mon_ROM_start ; Start at first address 171 00000004 172 00000004 ; Pack version & date into 32 bits 173 00000004 01025183 Version_ID DCD Maker*&1000000 + Version*&10000 + day*&8 00 + month*&80 + year 174 00000008 175 00000008 41 54 39 31 20 42 61 63 6B 2D 65 6E 64 20 6D 6F 6E 69 74 6F 72 2F 65 6D ARM Macro Assembler Page 21 75 6C 61 74 6F 72 20 76 65 72 73 69 6F 6E 20 30 2E 32 20 DCB "AT91 Back-end monitor/emulator version 0.2 " 176 00000033 4A 2E 20 47 61 72 73 69 64 65 2C 20 28 63 29 20 55 6E 69 76 65 72 73 69 74 79 20 6F 66 20 4D 61 6E 63 68 65 73 74 65 72 20 DCB "J. Garside, (c) University of Mancheste r " 177 0000005C 4D 61 72 63 68 20 32 30 30 33 DCB "March 2003" 178 00000066 179 00000066 00 00 ALIGN 180 00000068 181 00000068 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 182 00000068 183 00000068 FFFE0004 0C00C400 Mon_init_table DCD TC_base + TC_CHL0 + TC_CMR, &0C00C400 ; Wave, MCK/2 184 00000070 FFFE001C 00003E80 DCD TC_base + TC_CHL0 + TC_RC, 16000 ; /16000 185 00000078 FFFE0024 00000010 DCD TC_base + TC_CHL0 + TC_IER, &00000010 ; CPC interrupt 186 00000080 FFFE0028 000000EF DCD TC_base + TC_CHL0 + TC_IDR, &000000EF ; only 187 00000088 FFFE0000 00000005 DCD TC_base + TC_CHL0 + TC_CCR, 5 ; Start! 188 00000090 189 00000090 FFFD0008 00000001 DCD US0_base + US_IER, RxRdy ; Interrupt source(s) 190 00000098 191 00000098 ; channel #0 192 00000098 FFFFF134 08001748 DCD AIC_base + AIC_SPU, spurious_isr + ROM_b ase ; ROM 193 000000A0 FFFFF008 ARM Macro Assembler Page 22 00000024 DCD AIC_base + AIC_SMR2, &00000024 ; Edge triggered, pri. 4 194 000000A8 FFFFF010 00000023 DCD AIC_base + AIC_SMR4, &00000023 ; Edge triggered, pri. 3 195 000000B0 FFFFF020 00000022 DCD AIC_base + AIC_SMR8, &00000022 ; Edge triggered, pri. 2 196 000000B8 FFFFF088 080016FC DCD AIC_base + AIC_SVR2, Host_isr + ROM_ba se ; ROM 197 000000C0 FFFFF090 08001644 DCD AIC_base + AIC_SVR4, Timer0_isr + ROM_ba se ; ROM 198 000000C8 FFFFF0A0 0800168C DCD AIC_base + AIC_SVR8, PIO_isr + ROM_ba se ; ROM 199 000000D0 FFFFF120 00000114 DCD AIC_base + AIC_IECR, &00000114 ; PIO, TC0, US0 200 000000D8 201 000000D8 FFFF0040 DCD PIO_base + PIO_IER ; Data below ... 202 000000DC 000C0E00 DCD AT91_Spartan_IRQ :OR: AT91_Virtex_IRQ :O R: AT91_Ether_IRQ :OR: AT91_Spartan_init :OR: AT91_Virtex_init 203 000000E0 FFFF0004 00000100 DCD PIO_base + PIO_PDR, &00000100 ; TIOB2 output 204 000000E8 205 000000E8 FFFE0084 0C00C400 DCD TC_base + TC_CHL2 + TC_CMR, &0C00C400 ; Wave, MCK/2 206 000000F0 FFFE009C 00000008 DCD TC_base + TC_CHL2 + TC_RC, 8 ; Toggle @ 2MHz 207 000000F8 FFFE00A8 000000FF DCD TC_base + TC_CHL2 + TC_IDR, &000000FF ; No interrupts 208 00000100 FFFE0080 00000005 DCD TC_base + TC_CHL2 + TC_CCR, 5 ; Start! 209 00000108 210 00000108 FFFFFFFF DCD DEV_TERMINATE 211 0000010C 212 0000010C 213 0000010C Mon_init_table_RAM 214 0000010C FFFE0004 0C00C400 DCD TC_base + TC_CHL0 + TC_CMR, &0C00C400 ; Wave, MCK/2 215 00000114 FFFE001C 00003E80 DCD TC_base + TC_CHL0 + TC_RC, 16000 ; /16000 216 0000011C FFFE0024 00000010 DCD TC_base + TC_CHL0 + TC_IER, &00000010 ; CPC interrupt 217 00000124 FFFE0028 000000EF DCD TC_base + TC_CHL0 + TC_IDR, &000000EF ; only ARM Macro Assembler Page 23 218 0000012C FFFE0000 00000005 DCD TC_base + TC_CHL0 + TC_CCR, 5 ; Start! 219 00000134 220 00000134 FFFD0008 00000001 DCD US0_base + US_IER, RxRdy ; Interrupt source(s) 221 0000013C ; DCD US1_base + US_IER, RxRdy ; Interrupt source(s) 222 0000013C 223 0000013C ; channel #0 224 0000013C FFFFF134 00001374 DCD AIC_base + AIC_SPU, spurious_isr - RAM_i mage_start 225 00000144 FFFFF008 00000024 DCD AIC_base + AIC_SMR2, &00000024 ; Edge triggered, pri. 4 226 0000014C FFFFF010 00000023 DCD AIC_base + AIC_SMR4, &00000023 ; Edge triggered, pri. 3 227 00000154 FFFFF020 00000022 DCD AIC_base + AIC_SMR8, &00000022 ; Edge triggered, pri. 2 228 0000015C FFFFF088 00001328 DCD AIC_base + AIC_SVR2, Host_isr - RAM_im age_start 229 00000164 FFFFF090 00001270 DCD AIC_base + AIC_SVR4, Timer0_isr - RAM_im age_start 230 0000016C FFFFF0A0 000012B8 DCD AIC_base + AIC_SVR8, PIO_isr - RAM_im age_start 231 00000174 FFFFF120 00000114 DCD AIC_base + AIC_IECR, &00000114 ; PIO, TC0, US0 232 0000017C 233 0000017C FFFF0040 DCD PIO_base + PIO_IER ; Data below ... 234 00000180 000C0E00 DCD AT91_Spartan_IRQ :OR: AT91_Virtex_IRQ :O R: AT91_Ether_IRQ :OR: AT91_Spartan_init :OR: AT91_Virtex_init 235 00000184 FFFF0004 00000100 DCD PIO_base + PIO_PDR, &00000100 ; TIOB2 output 236 0000018C 237 0000018C FFFE0084 0C00C400 DCD TC_base + TC_CHL2 + TC_CMR, &0C00C400 ; Wave, MCK/2 238 00000194 FFFE009C 00000008 DCD TC_base + TC_CHL2 + TC_RC, 8 ; Toggle @ 2MHz 239 0000019C FFFE00A8 000000FF DCD TC_base + TC_CHL2 + TC_IDR, &000000FF ; No interrupts 240 000001A4 FFFE0080 00000005 DCD TC_base + TC_CHL2 + TC_CCR, 5 ; Start! 241 000001AC 242 000001AC FFFFFFFF DCD DEV_TERMINATE 243 000001B0 244 000001B0 ; ch. 1 245 000001B0 ; DCD AIC_base + AIC_SPU, spurious_isr + ROM_base ; ROM @@@ 246 000001B0 ; DCD AIC_base + AIC_SMR3, &00000024 ; Edge triggered, ARM Macro Assembler Page 24 pri. 4 247 000001B0 ; DCD AIC_base + AIC_SMR4, &00000023 ; Edge triggered, pri. 3 248 000001B0 ; DCD AIC_base + AIC_SVR3, Host_isr + ROM_base ; ROM @@ @ 249 000001B0 ; DCD AIC_base + AIC_SVR4, Timer0_isr + ROM_base ; ROM @@@ 250 000001B0 ; DCD AIC_base + AIC_IECR, &00000018 ; TC0, US1 251 000001B0 252 000001B0 00418937 Divisor_1kHz DCD &00418937 ; &100000000 * .001 253 000001B4 FFFE001C TC0_RC DCD TC_base + TC_CHL0 + TC_RC 254 000001B8 255 000001B8 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 256 000001B8 257 000001B8 RAM_image_length ; RAM area length 258 000001B8 00001FB0 DCD RAM_image_end - RAM_image_start 259 000001BC 00001390 Exec_RAM DCD execute_start - RAM_image_start 260 000001C0 000003F4 Comm_RAM DCD command_start - RAM_image_start 261 000001C4 262 000001C4 E1A0F00E First_SWI_instr mov pc, lr ; Return in supervisor mode 263 000001C8 E51FFF20 First_IRQ_instr ldr pc, [pc, #-&F20] ; Read from IVR instruction 264 000001CC 265 000001CC 266 000001CC Mon_ROM_start 267 000001CC ; tst r7, #Power_up_flag ; Power up reset? 268 000001CC ; stmneia r2, {r0-r9} ; make startup config visible if so 269 000001CC 270 000001CC E3A0A000 mov r10, #0 ; Ensure supervisor mode 271 000001D0 E51F0014 ldr r0, First_SWI_instr ; 272 000001D4 E58A0008 str r0, [r10, #&08] ; Plant return instruction 273 000001D8 EF000000 swi 0 ; 274 000001DC 275 000001DC E51F001C ldr r0, First_IRQ_instr ; 276 000001E0 E58A0018 str r0, [r10, #&18] ; Plant vector load 277 000001E4 278 000001E4 ; Beware: still want initial R2, R3, R8, R9, ... 279 000001E4 280 000001E4 E3A0A000 mov r10, #FALSE ; Shall we copy to RAM? 281 000001E8 E51F0038 ldr r0, RAM_image_length ; R1 holds Internal RAM size 282 000001EC E1500001 cmp r0, r1 ; Can fit in RAM? 283 000001F0 ; also allow user input @@ 284 000001F0 8A000008 bhi Mon_init_0 ; ARM Macro Assembler Page 25 285 000001F4 286 000001F4 E3E0A000 mov r10, #TRUE ; We will copy to RAM 287 000001F8 288 000001F8 E28F4C01 E2844F35 adrl r4, RAM_image_start ; Source 289 00000200 E3A01000 mov r1, #0 ; Destination 290 00000204 E1A00120 mov r0, r0, lsr #2 ; Length 291 00000208 292 00000208 E4945004 RAM_image_copy ldr r5, [r4], #4 ; 293 0000020C E4815004 str r5, [r1], #4 ; 294 00000210 E2500001 subs r0, r0, #1 ; 295 00000214 2AFFFFFB bhs RAM_image_copy ; Extra word included 296 00000218 297 00000218 E10F0000 Mon_init_0 mrs r0, cpsr ; Set up IRQ stack pointer 298 0000021C E3C0100F bic r1, r0, #Mode_bits ; Clear mode bits 299 00000220 E3811002 orr r1, r1, #IRQ_mode ; 300 00000224 E121F001 msr cpsr_c, r1 ; Go into IRQ mode 301 00000228 E1A00000 nop ; 302 0000022C E3A0DFF1 mov sp, #Int_stack - RAM_image_start 303 00000230 E121F000 msr cpsr_c, r0 ; Back to supervisor mode 304 00000234 E1A00000 nop ; 305 00000238 306 00000238 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 307 00000238 308 00000238 ; TEMPORARY CONFIG @@@ 309 00000238 ; bl XPIO_init ; 310 00000238 311 00000238 EB0004E4 bl Host_buffer_init ; Initialise serial rec eive buffer 312 0000023C EB000214 bl Terminal_init ; Initialise terminal feat ure 313 00000240 314 00000240 E37A0001 cmp r10, #TRUE ; 315 00000244 124F1C01 12411F39 adrnel r1, Mon_init_table ; Only ROM copy 316 0000024C 024F1C01 02411F12 adreql r1, Mon_init_table_RAM ; Point interrupts into RAM 317 00000254 318 00000254 E4916004 Mon_init1 ldr r6, [r1], #4 ; Register address 319 00000258 E3760001 cmp r6, #DEV_TERMINATE ; Terminator? 320 0000025C 0A000002 beq Mon_init2 ; yes - terminate 321 00000260 E4910004 ldr r0, [r1], #4 ; Get data value 322 00000264 E5860000 str r0, [r6] ; Store value 323 00000268 EAFFFFF9 b Mon_init1 ; and repeat ... 324 0000026C 325 0000026C E1A04829 Mon_init2 mov r4, r9, lsr #16 ; Upper bits of clock rate 326 00000270 E1A00809 mov r0, r9, lsl #16 ; Lower bits of clock rate ARM Macro Assembler Page 26 327 00000274 E51F10CC ldr r1, Divisor_1kHz ; MCK/1kHz 328 00000278 329 00000278 E3A05020 mov r5, #32 ; (r1 > &FFFF) => 16 real bi ts 330 0000027C 331 0000027C E1540001 div1 cmp r4, r1 ; 332 00000280 20444001 subhs r4, r4, r1 ; 333 00000284 E0B00000 adcs r0, r0, r0 ; Shift dividend & Acc 334 00000288 335 00000288 E2455001 sub r5, r5, #1 ; Count leaves carry alone 336 0000028C E1150005 tst r5, r5 ; 337 00000290 50A44004 adcpl r4, r4, r4 ; Top of shift register 338 00000294 5AFFFFF8 bpl div1 ; 339 00000298 340 00000298 E2800001 add r0, r0, #1 ; Round 341 0000029C E1B000A0 movs r0, r0, lsr #1 ; Always prescaled by 2 342 000002A0 ; beq ??? ; Trap for VERY slow @@@ 343 000002A0 344 000002A0 E51F10F4 ldr r1, TC0_RC ; Set timer to 1kHz 345 000002A4 E5810000 str r0, [r1] ; (regardless of Clock_rate) 346 000002A8 347 000002A8 E3A07038 mov r7, #shared_variables - Mon_RAM_start ; @@@ 348 000002AC EB000020 bl Interrupts_init ; Emulator interrupt set up 349 000002B0 ; Needs R7 set up 350 000002B0 351 000002B0 E10F0000 mrs r0, cpsr ; Enable interrupts 352 000002B4 E3C00080 bic r0, r0, #I_bit ; RAM image present by now 353 000002B8 E121F000 msr cpsr_c, r0 ; 354 000002BC 355 000002BC 356 000002BC ; Initialise memory and register definitions 357 000002BC 358 000002BC E3A01000 mov r1, #0 ; Mem start 359 000002C0 E5871020 str r1, [r7, #mem_area_start - shared_variab les] 360 000002C4 E5873024 str r3, [r7, #mem_area_end - shared_variable s] 361 000002C8 ; Covers all external RAM 362 000002C8 E5872028 str r2, [r7, #mem_area_pos - shared_variable s] 363 000002CC ; Offset 364 000002CC 365 000002CC E5878000 str r8, [r7, #Board_number - shared_variable s] 366 000002D0 E5879004 str r9, [r7, #Clock_rate - shared_variables] 367 000002D4 368 000002D4 ; For the present the register image is kept in static s pace 369 000002D4 ; It is still defined through a pointer 370 000002D4 E287906C add r9, r7, #reg_block - shared_variables 371 000002D8 ; Point at register space 372 000002D8 E587901C str r9, [r7, #reg_area_ptr - shared_variable s] 373 000002DC ; Save pointer ARM Macro Assembler Page 27 374 000002DC 375 000002DC ; Zero user's registers on power up @@@ 376 000002DC 377 000002DC ; Current set followed by banked registers for : User, S VC, ABT, UND, IRQ, FIQ 378 000002DC ; followed by 5 real SPSRs and one 'dustbin' SPSR 379 000002DC ; plus one word to make R15 visible 380 000002DC 381 000002DC E3A00000 mov r0, #0 ; Zero options (N.B. word) 382 000002E0 E587002C str r0, [r7, #Running_flags - shared_variabl es] 383 000002E4 384 000002E4 EB000028 bl Breakpoint_init ; 385 000002E8 EB000030 bl Watchpoint_init ; 386 000002EC 387 000002EC 388 000002EC E3A01F55 mov r1, #exec_variables - Mon_RAM_start 389 000002F0 ; Base of private variables 390 000002F0 391 000002F0 E3A00FE9 mov r0, #Exec_stack - RAM_image_start 392 000002F4 ; Base of execution stack 393 000002F4 E37A0001 cmp r10, #TRUE ; Are we in RAM? 394 000002F8 128FEB05 128EEF19 adrnel lr, execute_start ; Start of execution c ode (ROM) 395 00000300 051FE14C ldreq lr, Exec_RAM ; Start of execution code ( RAM) 396 00000304 E9205FFF stmfd r0!, {r0-r12, lr} ; Make room 397 00000308 E5810000 str r0, [r1, #exec_sp - exec_variables] ; Keep context 398 0000030C 399 0000030C E3A00FC1 mov r0, #Comm_stack - RAM_image_start 400 00000310 ; Base of command stack 401 00000310 128FEB01 128EEE0B adrnel lr, command_start ; Start of command cod e (ROM) 402 00000318 051FE160 ldreq lr, Comm_RAM ; Start of command code (RA M) 403 0000031C E9205FFF stmfd r0!, {r0-r12, lr} ; Make room 404 00000320 E5810004 str r0, [r1, #com_sp - exec_variables] ; Keep context 405 00000324 406 00000324 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 407 00000324 ; Initialise emulator's I/O @@@ 408 00000324 ; (If needed?) +++ 409 00000324 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 410 00000324 411 00000324 E37A0001 cmp r10, #TRUE ; Are we in RAM? 412 00000328 03A0F000 moveq pc, #0 ; If so jump to reset `vecto r' 413 0000032C EA000119 b main_loop ; Off we go! 414 00000330 415 00000330 ;------------------------------------------------------- ----------------------- 416 00000330 ; Set up for internal interrupt emulator 417 00000330 418 00000330 FFFF0000 ARM Macro Assembler Page 28 IO_PIO_base1 DCD PIO_base ; 419 00000334 420 00000334 E92D4003 Interrupts_init stmfd sp!, {r0-r1, lr} ; 421 00000338 422 00000338 E3A00000 mov r0, #0 ; Start at time 0 423 0000033C E5870008 str r0, [r7, #Line_time_clk - shared_variabl es] 424 00000340 E5C7000F strb r0, [r7, #interrupts_enable - shared_var iables] 425 00000344 ; Disable emulator interrupts 426 00000344 427 00000344 E5C70011 strb r0, [r7, #timer_compare - shared_variabl es] 428 00000348 ; Here? @@@ 429 00000348 430 00000348 E5C7000E strb r0, [r7, #interrupts_active - shared_var iables] 431 0000034C 432 0000034C E51FE024 ldr r14, IO_PIO_base1 ; Literal 433 00000350 E59E004C ldr r0, [r14, #PIO_ISR] ; Clear interrupt 434 00000354 E59E003C ldr r0, [r14, #PIO_PDSR] ; Read pin status 435 00000358 436 00000358 E3A01000 mov r1, #0 ; 437 0000035C E3100702 tst r0, #AT91_Virtex_init ; Test ports & translate 438 00000360 03811080 orreq r1, r1, #Int_L_button ; Active low 439 00000364 E3100701 tst r0, #AT91_Spartan_init ; 440 00000368 03811040 orreq r1, r1, #Int_R_button ; Active low 441 0000036C E3100B02 tst r0, #AT91_Ether_IRQ ; 442 00000370 13811008 orrne r1, r1, #Int_Ethernet ; Active high 443 00000374 E3100B01 tst r0, #AT91_Virtex_IRQ ; 444 00000378 03811004 orreq r1, r1, #Int_Virtex ; Active low (?) 445 0000037C E3100C02 tst r0, #AT91_Spartan_IRQ ; 446 00000380 03811002 orreq r1, r1, #Int_Spartan ; Active low (?) 447 00000384 E5C71010 strb r1, [r7, #Last_PIO_IRQ_state - shared_va riables] 448 00000388 ; Save pin state 449 00000388 450 00000388 ; initialise "interrupts_active" ? 451 00000388 452 00000388 ; Deal with Serial receiver etc. (?) @@@ 453 00000388 454 00000388 E8BD8003 ldmfd sp!, {r0-r1, pc} ; 455 0000038C 456 0000038C ;------------------------------------------------------- ----------------------- 457 0000038C 458 0000038C E92D400C Breakpoint_init stmfd sp!, {r2-r3, lr} ; 459 00000390 E3A03F5A mov r3, #breakpoint_table - Mon_RAM_start 460 00000394 E3A02008 mov r2, #breakpoint_max ; 461 00000398 E3A0E001 mov r14, #1 ; "Deleted" code 462 0000039C EA000000 b Brkpt_init_1 ; 463 000003A0 464 000003A0 E4C3E01C ARM Macro Assembler Page 29 Brkpt_init_lp strb r14, [r3], #brk_pt_rcd_length 465 000003A4 E2522001 Brkpt_init_1 subs r2, r2, #1 ; Loop entry 466 000003A8 2AFFFFFC bhs Brkpt_init_lp ; 467 000003AC E8BD800C ldmfd sp!, {r2-r3, pc} ; 468 000003B0 469 000003B0 ;------------------------------------------------------- ----------------------- 470 000003B0 471 000003B0 E92D400C Watchpoint_init stmfd sp!, {r2-r3, lr} ; 472 000003B4 E3A03F92 mov r3, #watchpoint_table - Mon_RAM_start 473 000003B8 E3A02001 mov r2, #watchpoint_max ; 474 000003BC E3A0E001 mov r14, #1 ; "Deleted" code 475 000003C0 EA000000 b Wchpt_init_1 ; 476 000003C4 477 000003C4 E4C3E01C Wchpt_init_lp strb r14, [r3], #wch_pt_rcd_length 478 000003C8 E2522001 Wchpt_init_1 subs r2, r2, #1 ; Loop entry 479 000003CC 2AFFFFFC bhs Wchpt_init_lp ; 480 000003D0 E8BD800C ldmfd sp!, {r2-r3, pc} ; 481 000003D4 482 000003D4 ;------------------------------------------------------- ----------------------- 483 000003D4 ;------------------------------------------------------- ----------------------- 484 000003D4 ; Monitor initial RAM image starts here 485 000003D4 486 000003D4 ; ALIGN Mon_RAM_image_position 487 000003D4 488 000003D4 RAM_image_start ; New label for RAM-ing code 489 000003D4 Mon_RAM_start 490 000003D4 EA0000EF b main_loop ; 491 000003D8 EAFFFFFE b . ; 492 000003DC EAFFFFFE b . ; 493 000003E0 EAFFFFFE b . ; 494 000003E4 EAFFFFFE b . ; 495 000003E8 EAFFFFFE b . ; 496 000003EC E51FFF20 ldr pc, [pc, #-&F20] ; Read from IVR 497 000003F0 EAFFFFFE b . ; 498 000003F4 499 000003F4 ;------------------------------------------------------- ----------------------- 500 000003F4 ; Variable space 501 000003F4 ;------------------------------------------------------- ----------------------- 502 000003F4 503 000003F4 00000000 Host_buffer_head DCD 0 ; 504 000003F8 00000000 Host_buffer_tail ARM Macro Assembler Page 30 DCD 0 ; 505 000003FC 00000000 00000000 00000000 00000000 Host_buffer_start DCD 0,0,0,0 ; 16 byte serial input buffe r 506 0000040C Host_buffer_end 507 0000040C 508 0000040C ; Place to stick variables 509 0000040C 510 0000040C shared_variables 511 0000040C 512 0000040C 00000000 Board_number DCD 0 ; Board serial number 513 00000410 00000000 Clock_rate DCD 0 ; Processor MCK speed <16>.< 16>MHz 514 00000414 ; Probably NOT needed @@@ 515 00000414 516 00000414 00000000 Line_time_clk DCD 0 ; Reserve words 517 00000418 518 00000418 00 arm_state DCB 0 ; Running, stopped etc. 519 00000419 00 arm_state_old DCB 0 ; Previous state when stoppe d 520 0000041A 521 0000041A 00 interrupts_active DCB 0 ; Internal interrupt request 522 0000041B 00 interrupts_enable DCB 0 ; Internal interrupt enables 523 0000041C 524 0000041C 00 Last_PIO_IRQ_state DCB 0 ; 525 0000041D 00 timer_compare DCB 0 ; 526 0000041E 00 Terminal_Rx_last DCB 0 ; Last state read from termi nal 527 0000041F 528 0000041F 00 ALIGN 529 00000420 530 00000420 00000000 arm_step_count DCD 0 ; Steps remaining - 0 = run 531 00000424 00000000 arm_instr_count DCD 0 ; Steps since last reset 532 00000428 533 00000428 00000000 reg_area_ptr DCD 0 ; Pointer to where registers ARM Macro Assembler Page 31 kept 534 0000042C 00000000 mem_area_start DCD 0 ; Start address 535 00000430 00000000 mem_area_end DCD 0 ; End address + 1 536 00000434 00000000 mem_area_pos DCD 0 ; Position 537 00000438 ;IO_area_start DCD 0 ; Start address 538 00000438 ;IO_area_end DCD 0 ; End address + 1 539 00000438 540 00000438 ; Compact these to one word? @@@ 541 00000438 00000000 Running_flags DCD 0 ; Enter SWI, BL, etc. 542 0000043C 00 break_enable DCB 0 ; Breakpoints should be enab led 543 0000043D 00 break_enabled DCB 0 ; Breakpoints are enabled 544 0000043E 545 0000043E 00 00 ALIGN 546 00000440 547 00000440 ; These are not really shared variables @@@ 548 00000440 00000000 Feature0_count DCD 0 ; Byte counts for feature do wnload 549 00000444 00000000 Feature1_count DCD 0 ; 550 00000448 00000000 Terminal_Rx_head DCD 0 ; 551 0000044C 00000000 Terminal_Rx_tail DCD 0 ; 552 00000450 00000000 Terminal_Tx_head DCD 0 ; 553 00000454 00000000 Terminal_Tx_tail DCD 0 ; 554 00000458 555 00000458 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Terminal_Rx_buff_start % Terminal_Rx_buff_length 556 00000468 Terminal_Rx_buff_end 557 00000468 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ARM Macro Assembler Page 32 00 Terminal_Tx_buff_start % Terminal_Tx_buff_length 558 00000478 Terminal_Tx_buff_end 559 00000478 ALIGN 560 00000478 561 00000478 562 00000478 ; Another 44 words of register variables 563 00000478 reg_block ; Registers kept here 564 00000478 ; Register storage offsets Check all numeric copies now purged @@@ 565 00000478 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 DCD 0, 0, 0, 0, 0, 0, 0, 0 ; R0-R7 566 00000498 00000000 00000000 00000000 00000000 00000000 sim_R8 DCD 0, 0, 0, 0, 0 ; Current R8-R12 567 000004AC 00000000 sim_R13 DCD 0 ; Current R13 568 000004B0 00000000 sim_R14 DCD 0 ; Current R14 569 000004B4 00000000 00000000 00000000 00000000 00000000 sim_R8_user DCD 0, 0, 0, 0, 0 ; User R8-R12 570 000004C8 00000000 00000000 sim_R13_user DCD 0, 0 ; User R13-R14 571 000004D0 00000000 00000000 sim_R13_svc DCD 0, 0 ; Supervisor R13-R14 572 000004D8 00000000 00000000 sim_R13_abt DCD 0, 0 ; Abort R13-R14 573 000004E0 00000000 00000000 sim_R13_undef DCD 0, 0 ; Undefined R13-R14 574 000004E8 00000000 00000000 sim_R13_IRQ DCD 0, 0 ; Interrupt R13-R14 575 000004F0 00000000 00000000 00000000 00000000 00000000 sim_R8_FIQ DCD 0, 0, 0, 0, 0 ; Fast Interrupt R8-R12 576 00000504 00000000 00000000 sim_R13_FIQ DCD 0, 0 ; Fast Interrupt R13-R14 577 0000050C 578 0000050C 00000000 ARM Macro Assembler Page 33 sim_SPSR_svc DCD 0 ; 37 579 00000510 00000000 sim_SPSR_abt DCD 0 ; 38 580 00000514 00000000 sim_SPSR_undef DCD 0 ; 39 581 00000518 00000000 sim_SPSR_irq DCD 0 ; 40 582 0000051C 00000000 sim_SPSR_fiq DCD 0 ; 41 583 00000520 584 00000520 00000000 sim_CPSR DCD 0 ; 42 585 00000524 00000000 sim_PC DCD 0 ; 43 586 00000528 587 00000528 588 00000528 exec_variables 589 00000528 590 00000528 00000000 exec_sp DCD 0 ; Emulator SP background sto re 591 0000052C 00000000 com_sp DCD 0 ; Interface SP background st ore 592 00000530 593 00000530 00000000 run_until_PC DCD 0 ; Variables used for running 594 00000534 00000000 run_until_SP DCD 0 ; subroutines during steppi ng 595 00000538 00000000 run_until_mode DCD 0 ; Byte #0; byte #1 used for old state 596 0000053C 597 0000053C 598 0000053C breakpoint_table 599 0000053C 600 0000053C ; Repeat record definition "breakpoint_max" times 601 0000053C BP_defn 602 0000053C 00 BP_active DCB 0 ; 603 0000053D 00 DCB 0 ; Padding 604 0000053E 00 BP_t DCB 0 ; Type 605 0000053F 00 BP_s DCB 0 ; Size 606 00000540 00000000 BP_aa DCD 0 ; 607 00000544 00000000 BP_ab DCD 0 ; 608 00000548 00000000 ARM Macro Assembler Page 34 BP_da DCD 0 ; 609 0000054C 00000000 BP_daH DCD 0 ; 610 00000550 00000000 BP_db DCD 0 ; 611 00000554 00000000 BP_dbH DCD 0 ; 612 00000558 BP_defn_end 613 00000558 614 00000558 0000001C brk_pt_rcd_length EQU BP_defn_end - BP_defn 615 00000558 616 00000558 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ARM Macro Assembler Page 35 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 % (breakpoint_max - 1) * brk_pt_rcd_length 617 0000061C ; Would you believe this as a define space directive?! 618 0000061C 619 0000061C breakpoint_table_end 620 0000061C 621 0000061C 00000002 BP_type EQU BP_t - breakpoint_table 622 0000061C 00000004 BP_addr_A EQU BP_aa - breakpoint_table 623 0000061C 00000008 BP_addr_B EQU BP_ab - breakpoint_table 624 0000061C 0000000C BP_data_A EQU BP_da - breakpoint_table 625 0000061C 00000014 BP_data_B EQU BP_db - breakpoint_table 626 0000061C 627 0000061C 628 0000061C watchpoint_table 629 0000061C 630 0000061C ; Repeat record definition "watchpoint_max" times 631 0000061C WP_defn 632 0000061C 00 WP_active DCB 0 ; 633 0000061D 00 DCB 0 ; Padding 634 0000061E 00 WP_t DCB 0 ; Type 635 0000061F 00 WP_s DCB 0 ; Size 636 00000620 00000000 WP_aa DCD 0 ; 637 00000624 00000000 WP_ab DCD 0 ; 638 00000628 00000000 WP_da DCD 0 ; 639 0000062C 00000000 WP_daH DCD 0 ; 640 00000630 00000000 WP_db DCD 0 ; ARM Macro Assembler Page 36 641 00000634 00000000 WP_dbH DCD 0 ; 642 00000638 WP_defn_end 643 00000638 644 00000638 0000001C wch_pt_rcd_length EQU WP_defn_end - WP_defn 645 00000638 646 00000638 % (watchpoint_max - 1) * wch_pt_rcd_length 647 00000638 ; Would you believe this as a define space directive?! 648 00000638 649 00000638 watchpoint_table_end 650 00000638 651 00000638 00000002 WP_type EQU WP_t - watchpoint_table 652 00000638 00000004 WP_addr_A EQU WP_aa - watchpoint_table 653 00000638 00000008 WP_addr_B EQU WP_ab - watchpoint_table 654 00000638 0000000C WP_data_A EQU WP_da - watchpoint_table 655 00000638 00000014 WP_data_B EQU WP_db - watchpoint_table 656 00000638 657 00000638 Mon_RAM_end 658 00000638 659 00000638 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ARM Macro Assembler Page 37 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 % Comm_stack_length * 4 660 000006D8 Comm_stack 661 000006D8 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ARM Macro Assembler Page 38 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 % Exec_stack_length * 4 662 00000778 Exec_stack 663 00000778 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 % Int_stack_length * 4 664 00000798 Int_stack 665 00000798 666 00000798 ;------------------------------------------------------- ----------------------- 667 00000798 ; RAM-ed code 668 00000798 ;------------------------------------------------------- ----------------------- 669 00000798 670 00000798 E3A00F55 main_loop mov r0, #exec_variables - Mon_RAM_start 671 0000079C E590D000 ldr sp, [r0, #exec_sp - exec_variables] 672 000007A0 ; Swap in execution context 673 000007A0 E8BD9FFF ldmfd sp!, {r0-r12, pc} ; No flags or owt @@@ 674 000007A4 675 000007A4 ; Emulator runs one step 676 000007A4 677 000007A4 E92D5FFF deschedule_ex stmfd sp!, {r0-r12, lr} ; Save scratch & user SP 678 000007A8 679 000007A8 E3A00F55 mov r0, #exec_variables - Mon_RAM_start 680 000007AC E580D000 str sp, [r0, #exec_sp - exec_variables] 681 000007B0 ; Swap out execution context 682 000007B0 ARM Macro Assembler Page 39 683 000007B0 E590D004 ldr sp, [r0, #com_sp - exec_variables] 684 000007B4 ; Swap in command context 685 000007B4 E8BD9FFF ldmfd sp!, {r0-r12, pc} ; No flags @@@ 686 000007B8 687 000007B8 ; Monitor processes any pending bytes 688 000007B8 689 000007B8 E92D5FFF deschedule_com stmfd sp!, {r0-r12, lr} ; Save scratch & user SP 690 000007BC 691 000007BC E3A00F55 mov r0, #exec_variables - Mon_RAM_start 692 000007C0 E580D004 str sp, [r0, #com_sp - exec_variables] 693 000007C4 ; Swap out command context 694 000007C4 695 000007C4 EAFFFFF3 b main_loop ; Forever! 696 000007C8 697 000007C8 ;------------------------------------------------------- ----------------------- 698 000007C8 ;------------------------------------------------------- ----------------------- 699 000007C8 700 000007C8 E3A07038 command_start mov r7, #shared_variables - Mon_RAM_start 701 000007CC 702 000007CC EB00038F command_loop bl Host_in ; Get command 703 000007D0 704 000007D0 E21010C0 ands r1, r0, #&C0 ; Split on top 2 bits - set flags 705 000007D4 E200003F and r0, r0, #&3F ; Lose `class' bits 706 000007D8 0A000003 beq Command_monitor ; 00-3F 707 000007DC E3510080 cmp r1, #&80 ; 708 000007E0 3A000066 blo Command_memory ; 40-7F 709 000007E4 0A000075 beq Command_run ; 80-BF 710 000007E8 EA000084 b Command_reserved ; C0-FF 711 000007EC 712 000007EC 713 000007EC E7DF1220 Command_monitor ldrb r1, [pc, r0, lsr #4] ; Divide on bits 5..4 714 000007F0 E08FF101 add pc, pc, r1, lsl #2 ; 715 000007F4 716 000007F4 00 DCB (Monitor_ctrl - %f1) / 4 ; 00-0F 717 000007F5 09 DCB (Monitor_load - %f1) / 4 ; 10-1F 718 000007F6 13 DCB (Monitor_enq - %f1) / 4 ; 20-2F 719 000007F7 1C DCB (Monitor_brk - %f1) / 4 ; 30-3F 720 000007F8 1 ; Label after first word 721 000007F8 722 000007F8 E200000F Monitor_ctrl and r0, r0, #&0F ; 723 000007FC E3500005 cmp r0, #(%f11 - %f10) / 2 ; 724 00000800 2AFFFFF1 bhs command_loop ; Ignore if out of range 725 00000804 726 00000804 E1A00080 mov r0, r0, lsl #1 ; ARM Macro Assembler Page 40 727 00000808 E19F00F0 ldrsh r0, [pc, r0] ; 728 0000080C E08FF000 add pc, pc, r0 ; 729 00000810 730 00000810 10 731 00000810 EC 01 DCW Nop - %f1 ; 0 732 00000812 F0 01 DCW Ping - %f1 ; 1 733 00000814 1 734 00000814 00 02 DCW Enq - %b1 ; 2 735 00000816 B8 FF DCW command_loop - %b1 ; 3 - not defined 736 00000818 60 02 DCW Reset_proc - %b1 ; 4 737 0000081A 11 738 0000081A 00 00 ALIGN 739 0000081C 740 0000081C E200100F Monitor_load and r1, r0, #&0F ; Remains of command 741 00000820 EB00037A bl Host_in ; Feature number 742 00000824 743 00000824 E3510006 cmp r1, #(%f11 - %f10) / 2 ; 744 00000828 2AFFFFE7 bhs command_loop ; Ignore if out of range 745 0000082C 746 0000082C E1A01081 mov r1, r1, lsl #1 ; 747 00000830 E19F10F1 ldrsh r1, [pc, r1] ; 748 00000834 E08FF001 add pc, pc, r1 ; 749 00000838 750 00000838 10 751 00000838 44 02 DCW Dld_get_status - %f1 ; 0 752 0000083A 50 02 DCW Dld_set_status - %f1 ; 1 753 0000083C 1 754 0000083C 7C 02 DCW Send_message - %b1 ; 2 755 0000083E E4 02 DCW Get_message - %b1 ; 3 756 00000840 44 03 DCW Dld_header - %b1 ; 4 757 00000842 64 03 DCW Dld_packet - %b1 ; 5 758 00000844 11 759 00000844 ALIGN 760 00000844 761 00000844 E200000F Monitor_enq and r0, r0, #&0F ; 762 00000848 E3500006 cmp r0, #(%f11 - %f10) / 2 ; 763 0000084C 2AFFFFDE bhs command_loop ; Ignore if out of range 764 00000850 765 00000850 E1A00080 mov r0, r0, lsl #1 ; 766 00000854 E19F00F0 ldrsh r0, [pc, r0] ; 767 00000858 E08FF000 add pc, pc, r0 ; 768 0000085C 769 0000085C 10 770 0000085C 00 05 DCW Proc_status - %f1 ; 0 771 0000085E 68 04 DCW Proc_stop - %f1 ; 1 772 00000860 1 773 00000860 68 04 DCW Proc_pause - %b1 ; 2 774 00000862 84 04 DCW Proc_continue - %b1 ; 3 775 00000864 BC 04 DCW Proc_set_flags - %b1 ; 4 776 00000866 E0 04 DCW Proc_get_flags - %b1 ; 5 777 00000868 11 778 00000868 779 00000868 E200100D Monitor_brk and r1, r0, #&0D ; Remains of command ARM Macro Assembler Page 41 780 0000086C 781 0000086C E3110004 tst r1, #&04 ; Only brk or wch so far @@@ 782 00000870 ; Initialise with appropriate tables 783 00000870 03A03F5A moveq r3, #breakpoint_table - Mon_RAM_start 784 00000874 13A03F92 movne r3, #watchpoint_table - Mon_RAM_start 785 00000878 03A06008 moveq r6, #breakpoint_max ; Spare regisiter 786 0000087C 13A06001 movne r6, #watchpoint_max ; Spare regisiter 787 00000880 03A0401C moveq r4, #brk_pt_rcd_length ; Number of bytes in definition 788 00000884 13A0401C movne r4, #wch_pt_rcd_length ; Number of bytes in definition 789 00000888 790 00000888 E3100002 tst r0, #&02 ; Definition or activation? 791 0000088C 1A000017 bne Monitor_brk_act ; 792 00000890 793 00000890 EB00035E bl Host_in ; Breakpoint number 794 00000894 E1A02000 mov r2, r0 ; 795 00000898 796 00000898 E0233294 mla r3, r4, r2, r3 ; Find definition start 797 0000089C 798 0000089C E2444002 sub r4, r4, #2 ; Bodge for word alignment @ @@ 799 000008A0 E2833002 add r3, r3, #2 ; (Shouldn't really be a byt e stream) @@@ 800 000008A4 801 000008A4 E3110001 tst r1, #&01 ; 0 = write, 1 = read 802 000008A8 1A000009 bne Monitor_brk_rd ; 803 000008AC 804 000008AC E5530002 ldrb r0, [r3, #-2] ; Check existing state 805 000008B0 E3500001 cmp r0, #1 ; "Deleted"? 806 000008B4 03A00003 moveq r0, #3 ; Activate if so 807 000008B8 05430002 streqb r0, [r3, #-2] ; Set breakpoint state 808 000008BC 809 000008BC EB000353 Monitor_brk_wr bl Host_in ; Get byte 810 000008C0 811 000008C0 E1520006 cmp r2, r6 ; # < maximum? 812 000008C4 34C30001 strlob r0, [r3], #1 ; Save if it is 813 000008C8 E2544001 subs r4, r4, #1 ; 814 000008CC 8AFFFFFA bhi Monitor_brk_wr ; 815 000008D0 816 000008D0 EAFFFFBD b command_loop ; 817 000008D4 818 000008D4 819 000008D4 E1520006 Monitor_brk_rd cmp r2, r6 ; # < maximum? 820 000008D8 34D30001 ldrlob r0, [r3], #1 ; Get if it is 821 000008DC 23A00000 movhs r0, #0 ; Zero if it isn't 822 000008E0 823 000008E0 EB000341 bl Host_out ; Send byte 824 000008E4 E2544001 subs r4, r4, #1 ; 825 000008E8 8AFFFFF9 bhi Monitor_brk_rd ; 826 000008EC 827 000008EC EAFFFFB6 b command_loop ; 828 000008F0 829 000008F0 ARM Macro Assembler Page 42 830 000008F0 E3110001 Monitor_brk_act tst r1, #&01 ; 0 = write, 1 = read 831 000008F4 1A000011 bne Monitor_brk_stat ; 832 000008F8 833 000008F8 EB00031A bl Host_get_word ; Write activation bits 834 000008FC E1A05000 mov r5, r0 ; 835 00000900 EB000318 bl Host_get_word ; 836 00000904 E1A02000 mov r2, r0 ; 837 00000908 838 00000908 E1160006 tst r6, r6 ; (breakpoint_max) 839 0000090C 0AFFFFAE beq command_loop ; If no breakpoints are inc luded 840 00000910 841 00000910 E3A00000 Monitor_brk_wr1 mov r0, #0 ; 842 00000914 E1B050A5 movs r5, r5, lsr #1 ; 843 00000918 E0A00000 adc r0, r0, r0 ; 844 0000091C E1B020A2 movs r2, r2, lsr #1 ; 845 00000920 E0B00000 adcs r0, r0, r0 ; 846 00000924 15D31000 ldrneb r1, [r3] ; 847 00000928 13110002 tstne r1, #2 ; Test if defined 848 0000092C 15C30000 strneb r0, [r3] ; Store if (still) non-zero 849 00000930 E0833004 add r3, r3, r4 ; Always move on 850 00000934 E2566001 subs r6, r6, #1 ; 851 00000938 8AFFFFF4 bhi Monitor_brk_wr1 ; 852 0000093C 853 0000093C EAFFFFA2 b command_loop ; 854 00000940 855 00000940 856 00000940 ; Splits flags into 2 words; returns 00 for unimplemente d breakpoints 857 00000940 Monitor_brk_stat 858 00000940 E2562001 subs r2, r6, #1 ; Offset of last entry 859 00000944 4A000009 bmi Monitor_brk_stat_out ; No breakpoints allowed 860 00000948 E0060492 mul r6, r2, r4 ; Offset to last entry 861 0000094C E3A00000 mov r0, #0 ; Initialise accumulators 862 00000950 E3A02000 mov r2, #0 ; 863 00000954 864 00000954 Monitor_brk_stat_loop 865 00000954 E7D35006 ldrb r5, [r3, r6] ; (a.k.a. "BP_active") 866 00000958 E1150125 tst r5, r5, lsr #2 ; Bit 1 into carry 867 0000095C E0A00000 adc r0, r0, r0 ; Accumulate 868 00000960 E11500A5 tst r5, r5, lsr #1 ; Bit 0 into carry 869 00000964 E0A22002 adc r2, r2, r2 ; Accumulate 870 00000968 E0566004 subs r6, r6, r4 ; 871 0000096C 2AFFFFF8 bcs Monitor_brk_stat_loop ; Continue (?) 872 00000970 873 00000970 Monitor_brk_stat_out 874 00000970 EB000309 bl Host_put_word ; 875 00000974 E1A00002 mov r0, r2 ; 876 00000978 EB000307 bl Host_put_word ; 877 0000097C 878 0000097C EAFFFF92 b command_loop ; 879 00000980 880 00000980 ; @@@ adr lr,.. and jump (??) 881 00000980 ARM Macro Assembler Page 43 882 00000980 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 883 00000980 884 00000980 E1A01000 Command_memory mov r1, r0 ; Command 885 00000984 EB0002F7 bl Host_get_word ; 886 00000988 E1A02000 mov r2, r0 ; Address 887 0000098C EB000309 bl Host_get_halfword ; 888 00000990 E1B03000 movs r3, r0 ; Length 889 00000994 0AFFFF8C beq command_loop ; Length = 0 890 00000998 891 00000998 E2110030 ands r0, r1, #&30 ; Address space 892 0000099C 0A000004 beq Memory_IO ; 893 000009A0 E3500020 cmp r0, #&20 ; 894 000009A4 2AFFFF88 bhs command_loop ; Unimplemented space 895 000009A8 ; else registers 896 000009A8 897 000009A8 E3110008 tst r1, #&08 ; Direction bit 898 000009AC 1A000104 bne Get_reg ; Read 899 000009B0 EA000113 b Put_reg ; Write 900 000009B4 901 000009B4 902 000009B4 E3110008 Memory_IO tst r1, #&08 ; Direction bit 903 000009B8 1A000120 bne Get_mem ; Read 904 000009BC EA000143 b Put_mem ; Write 905 000009C0 906 000009C0 907 000009C0 E200103F Command_run and r1, r0, #&3F ; Command vector 908 000009C4 909 000009C4 ; Does anything want inverting? @@@ 910 000009C4 E5C7102C strb r1, [r7, #Running_flags - shared_variab les] 911 000009C8 ; Save flags for BL, SWI service, breakpoints etc. 912 000009C8 913 000009C8 E3110010 tst r1, #Run_B_bit ; Breakpoints 914 000009CC 03A00000 moveq r0, #FALSE ; Disable breakpoints 915 000009D0 13E00000 movne r0, #TRUE ; Enable breakpoints 916 000009D4 E5C70030 strb r0, [r7, #break_enable - shared_variabl es] 917 000009D8 918 000009D8 ; The following allows single step sequences to detect b reakpoints 919 000009D8 E3110001 tst r1, #Run_BB_bit ; Breakpoint on first in str. too 920 000009DC 03A00000 moveq r0, #FALSE ; Disable breakpoints 921 000009E0 13E00000 movne r0, #TRUE ; Enable breakpoints 922 000009E4 E5C70031 strb r0, [r7, #break_enabled - shared_variab les] 923 000009E8 924 000009E8 EB0002DE bl Host_get_word ; Number of steps 925 000009EC E5870014 str r0, [r7, #arm_step_count - shared_variab les] 926 000009F0 ; Set step count 927 000009F0 E3500000 cmp r0, #0 ; 0 steps => "run" ARM Macro Assembler Page 44 928 000009F4 03A00080 moveq r0, #State_running ; Set status to run 929 000009F8 13A000C0 movne r0, #State_stepping ; Set status to step 930 000009FC E5C7000C strb r0, [r7, #arm_state - shared_variables] 931 00000A00 ; Signal to processor 932 00000A00 933 00000A00 ; Extra entry point here save a word 934 00000A00 Command_reserved ; Do nothing for now 935 00000A00 EAFFFF71 Nop b command_loop ; 936 00000A04 ; No operation - can be used for padding to resync. 937 00000A04 938 00000A04 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 939 00000A04 ; Resychronise 940 00000A04 941 00000A04 E59F0004 Ping ldr r0, Ping_answer ; 942 00000A08 E24FEF91 adr lr, command_loop ; 943 00000A0C EA0002E2 b Host_put_word ; 944 00000A10 945 00000A10 4F 4B 30 30 Ping_answer DCB "OK00" ; One word 946 00000A14 947 00000A14 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 948 00000A14 ; Provide board information 949 00000A14 950 00000A14 E28F1048 Enq adr r1, enq_message ; 951 00000A18 E0D120B2 ldrh r2, [r1], #2 ; Length of `auxiliary' mes sage 952 00000A1C 953 00000A1C E3A00001 mov r0, #1 ; Number of memory segments @@@ 954 00000A20 ; As map is static could shrink this code @@@ 955 00000A20 956 00000A20 E1A00180 mov r0, r0, lsl #3 ; Each memory segment is 8 bytes 957 00000A24 E2800001 add r0, r0, #1 ; One more for the number 958 00000A28 E0800002 add r0, r0, r2 ; Total number of bytes in m essage 959 00000A2C EB0002D7 bl Host_put_halfword ; Message length in bytes 960 00000A30 961 00000A30 E4D10001 Enq1 ldrb r0, [r1], #1 ; Send message 962 00000A34 EB0002EC bl Host_out ; 963 00000A38 964 00000A38 E2522001 subs r2, r2, #1 ; 965 00000A3C 1AFFFFFB bne Enq1 ; 966 00000A40 967 00000A40 E3A00001 mov r0, #1 ; Memory segments @@@ 968 00000A44 969 00000A44 EB0002E8 bl Host_out ; 970 00000A48 971 00000A48 E5971020 ldr r1, [r7, #mem_area_start - shared_variab les] ARM Macro Assembler Page 45 972 00000A4C E1A00001 mov r0, r1 ; Memory start address 973 00000A50 EB0002D1 bl Host_put_word ; 974 00000A54 E5972024 ldr r2, [r7, #mem_area_end - shared_variable s] 975 00000A58 E0420001 sub r0, r2, r1 ; Memory segment length 976 00000A5C EB0002CE bl Host_put_word ; 977 00000A60 978 00000A60 ; any more? @@@ 979 00000A60 980 00000A60 EAFFFF59 b command_loop ; 981 00000A64 982 00000A64 0D 00 enq_message DCW %f3-%f1 ; Length of this part 983 00000A66 1 984 00000A66 01 00 00 DCB 1, 0, 0 ; ARM type, subtype 985 00000A69 03 DCB (%f3-%f2)/3 ; Additional features 986 00000A6A 2 987 00000A6A 11 01 0A DCB &11, 1, 10 ; Spartan 10 PQ100 988 00000A6D IF Virtex_E 989 00000A6D 13 02 1E DCB &13, 2, 30 ; Virtex 300E PQ240 990 00000A70 ELSE 992 ENDIF 993 00000A70 ; Should check for presence really @@@ 994 00000A70 00 08 00 DCB &00, 8, 0 ; Terminal = #2 995 00000A73 ; See "terminal_feature" @@@ 996 00000A73 3 997 00000A73 00 ALIGN 998 00000A74 999 00000A74 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1000 00000A74 ; Soft reset request 1001 00000A74 1002 00000A74 E3A00002 Reset_proc mov r0, #State_to_reset ; Reset state request 1003 00000A78 E5C7000C strb r0, [r7, #arm_state - shared_variables] 1004 00000A7C ; Signal to processor 1005 00000A7C 1006 00000A7C EAFFFF52 b command_loop ; 1007 00000A80 1008 00000A80 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1009 00000A80 ; Feature number in R0 1010 00000A80 1011 00000A80 Dld_get_status 1012 00000A80 E3A00000 mov r0, #0 ; @@@ 1013 00000A84 EB0002C4 bl Host_put_word ; 1014 00000A88 EAFFFF4F b command_loop ; 1015 00000A8C 1016 00000A8C Dld_set_status 1017 00000A8C EB0002B5 bl Host_get_word ; @@@ 1018 00000A90 EAFFFF4D b command_loop ; 1019 00000A94 1020 00000A94 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1021 00000A94 ; This buffer post-increments head and tail. 1022 00000A94 ; Pointers become equal when buffer is empty. 1023 00000A94 ARM Macro Assembler Page 46 1024 00000A94 E92D4001 Terminal_init stmfd sp!, {r0, lr} ; 1025 00000A98 E3A0E074 mov r14, #Terminal_Rx_head - Mon_RAM_start 1026 00000A9C ; Crude hack method for now @@@ 1027 00000A9C E3A00084 mov r0, #Terminal_Rx_buff_start - Mon_RAM_st art 1028 00000AA0 E58E0000 str r0, [r14] ; Initialise Rx head 1029 00000AA4 E58E0004 str r0, [r14, #Terminal_Rx_tail - Terminal_R x_head] 1030 00000AA8 ; Initialise Rx tail 1031 00000AA8 1032 00000AA8 E3A00094 mov r0, #Terminal_Tx_buff_start - Mon_RAM_st art 1033 00000AAC E58E0008 str r0, [r14, #Terminal_Tx_head - Terminal_R x_head] 1034 00000AB0 ; Initialise Tx head 1035 00000AB0 E58E000C str r0, [r14, #Terminal_Tx_tail - Terminal_R x_head] 1036 00000AB4 ; Initialise Tx tail 1037 00000AB4 E8BD8001 ldmfd sp!, {r0, pc} ; 1038 00000AB8 1039 00000AB8 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1040 00000AB8 1041 00000AB8 ; This means we -receive- 1042 00000AB8 E1A01000 Send_message mov r1, r0 ; Feature number 1043 00000ABC EB0002D3 bl Host_in ; Length of message 1044 00000AC0 E3A03000 mov r3, #0 ; Count of bytes accepted 1045 00000AC4 E1B02000 movs r2, r0 ; Can send 0 bytes to wrong feature 1046 00000AC8 0A000011 beq Send_message3 ; Always answers 00 1047 00000ACC 1048 00000ACC E597403C ldr r4, [r7, #Terminal_Rx_head - shared_vari ables] 1049 00000AD0 E5975040 ldr r5, [r7, #Terminal_Rx_tail - shared_vari ables] 1050 00000AD4 1051 00000AD4 EB0002CD Send_message1 bl Host_in ; Get byte 1052 00000AD8 E3510002 cmp r1, #Terminal_feature ; Should we bother? 1053 00000ADC 1A000006 bne Send_message2 ; no - discard 1054 00000AE0 E284E001 add r14, r4, #1 ; Look ahead 1055 00000AE4 E35E0094 cmp r14, #Terminal_Rx_buff_end - Mon_RAM_sta rt 1056 00000AE8 23A0E084 movhs r14, #Terminal_Rx_buff_start - Mon_RAM_s tart 1057 00000AEC E15E0005 cmp r14, r5 ; Caught tail pointer? 1058 00000AF0 15C40000 strneb r0, [r4] ; Place in byte buffer if no t 1059 00000AF4 11A0400E movne r4, r14 ; update pointer 1060 00000AF8 12833001 addne r3, r3, #1 ; and add to acknowledgemen t 1061 00000AFC E2522001 Send_message2 ARM Macro Assembler Page 47 subs r2, r2, #1 ; Count byte in whatever 1062 00000B00 8AFFFFF3 bhi Send_message1 ; 1063 00000B04 1064 00000B04 E5D7000E ldrb r0, [r7, #interrupts_active - shared_var iables] 1065 00000B08 E3800010 orr r0, r0, #Int_Rx_ready ; Set interrupt bit 1066 00000B0C ; Next two instructions atomic 1067 00000B0C E5C7000E strb r0, [r7, #interrupts_active - shared_var iables] 1068 00000B10 E587403C str r4, [r7, #Terminal_Rx_head - shared_vari ables] 1069 00000B14 1070 00000B14 E1A00003 Send_message3 mov r0, r3 ; Ack with No. of bytes acce pted 1071 00000B18 EB0002B3 bl Host_out ; 1072 00000B1C EAFFFF2A b command_loop ; 1073 00000B20 1074 00000B20 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1075 00000B20 1076 00000B20 ; This means we -send- 1077 00000B20 E1A01000 Get_message mov r1, r0 ; Feature number 1078 00000B24 EB0002B9 bl Host_in ; Max. length of message 1079 00000B28 E3510002 cmp r1, #Terminal_feature ; 1080 00000B2C 13A00000 movne r0, #0 ; Zero if not talking to ter minal 1081 00000B30 1082 00000B30 E5971044 ldr r1, [r7, #Terminal_Tx_head - shared_vari ables] 1083 00000B34 E5972048 ldr r2, [r7, #Terminal_Tx_tail - shared_vari ables] 1084 00000B38 E0511002 subs r1, r1, r2 ; Find occupancy 1085 00000B3C 42811010 addmi r1, r1, #Terminal_Tx_buff_end - Terminal _Tx_buff_start 1086 00000B40 E1500001 cmp r0, r1 ; Requested length > current ly available? 1087 00000B44 81A00001 movhi r0, r1 ; Get lesser length 1088 00000B48 1089 00000B48 EB0002A7 bl Host_out ; Send transmission length 1090 00000B4C E1B03000 movs r3, r0 ; 1091 00000B50 0AFFFF1D beq command_loop ; Quit if nothing to send 1092 00000B54 1093 00000B54 E4D20001 Get_message1 ldrb r0, [r2], #1 ; Get byte, post increment 1094 00000B58 EB0002A3 bl Host_out ; and send 1095 00000B5C E35200A4 cmp r2, #Terminal_Tx_buff_end - Mon_RAM_star t 1096 00000B60 23A02094 movhs r2, #Terminal_Tx_buff_start - Mon_RAM_st art 1097 00000B64 E2533001 subs r3, r3, #1 ; 1098 00000B68 8AFFFFF9 bhi Get_message1 ; 1099 00000B6C 1100 00000B6C E5D7000E ldrb r0, [r7, #interrupts_active - shared_var ARM Macro Assembler Page 48 iables] 1101 00000B70 E3800020 orr r0, r0, #Int_Tx_ready ; Set interrupt bit 1102 00000B74 ; Next two instructions atomic 1103 00000B74 E5C7000E strb r0, [r7, #interrupts_active - shared_var iables] 1104 00000B78 E5872048 str r2, [r7, #Terminal_Tx_tail - shared_vari ables] 1105 00000B7C 1106 00000B7C EAFFFF12 b command_loop ; 1107 00000B80 1108 00000B80 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1109 00000B80 1110 00000B80 E1A01000 Dld_header mov r1, r0 ; Feature number 1111 00000B84 EB000277 bl Host_get_word ; Length of file to follow 1112 00000B88 1113 00000B88 E2872034 add r2, r7, #Feature0_count - shared_variabl es 1114 00000B8C E7820101 str r0, [r2, r1, lsl #2] ; Save download count 1115 00000B90 1116 00000B90 E3510001 cmp r1, #1 ; No jump table - (compresse d) 1117 00000B94 3A00000F blo Spartan_header ; 0 1118 00000B98 0A00001E beq Virtex_header ; 1 1119 00000B9C EA00000B b Dld_no_such_feature ; >= 2 1120 00000BA0 1121 00000BA0 1122 00000BA0 E1A01000 Dld_packet mov r1, r0 ; Feature number 1123 00000BA4 EB000299 bl Host_in ; Length of block to follow 1124 00000BA8 1125 00000BA8 E1B02000 movs r2, r0 ; Convert 0 to 256 1126 00000BAC 03A02C01 moveq r2, #&100 ; Length now in R2 1127 00000BB0 1128 00000BB0 E2873034 add r3, r7, #Feature0_count - shared_variabl es 1129 00000BB4 E0833101 add r3, r3, r1, lsl #2 ; Point at global counter 1130 00000BB8 1131 00000BB8 E3510001 cmp r1, #1 ; Feature number 1132 00000BBC 3A00002A blo Spartan_packet ; 0 1133 00000BC0 0A000025 beq Virtex_packet ; 1 1134 00000BC4 ; >= 2 fall into ... 1135 00000BC4 1136 00000BC4 ; The following deals with undefined features 1137 00000BC4 Dld_no_such_feature_pkt 1138 00000BC4 EB000291 bl Host_in ; Waste characters 1139 00000BC8 E2522001 subs r2, r2, #1 ; 1140 00000BCC 8AFFFFFC bhi Dld_no_such_feature_pkt ; 1141 00000BD0 1142 00000BD0 Dld_no_such_feature 1143 00000BD0 E3A0004E mov r0, #"N" ; Indicate failure 1144 00000BD4 EA000039 b FPGA_pkt_outN ; ARM Macro Assembler Page 49 1145 00000BD8 1146 00000BD8 ;------------------------------------------------------- ----------------------- 1147 00000BD8 ; These ought to know about the presence/absence of the devices @@@ 1148 00000BD8 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1149 00000BD8 ; Corrupts R0, R1 1150 00000BD8 1151 00000BD8 E59F0928 Spartan_header ldr r0, IO_PIO_base ; 1152 00000BDC 1153 00000BDC ; Force other PIO bits to correct state before resetting Spartan 1154 00000BDC E3A01502 mov r1, #AT91_Spartan_CS1 ; 1155 00000BE0 E5801030 str r1, [r0, #PIO_SODR] ; Output high (alway s PIO output) 1156 00000BE4 1157 00000BE4 E3A01A03 mov r1, #(AT91_Spartan_HDC :OR: AT91_FPGA_ba ud) 1158 00000BE8 E5801014 str r1, [r0, #PIO_ODR] ; Output disabled 1159 00000BEC E5801000 str r1, [r0, #PIO_PER] ; Ensure PIO is used 1160 00000BF0 ; Sensitive signals floated 1161 00000BF0 1162 00000BF0 E3A01801 mov r1, #AT91_Spartan_prog ; Reset Spartan 1163 00000BF4 E5801034 str r1, [r0, #PIO_CODR] ; Programme pin low 1164 00000BF8 1165 00000BF8 E3A02008 mov r2, #8 ; Delay iterations 1166 00000BFC E2522001 spartan_hdr0 subs r2, r2, #1 ; Leave pin low for a while 1167 00000C00 8AFFFFFD bhi spartan_hdr0 ; (>300ns) 1168 00000C04 1169 00000C04 E5801030 str r1, [r0, #PIO_SODR] ; Programme pin high again 1170 00000C08 1171 00000C08 E590103C spartan_hdr1 ldr r1, [r0, #PIO_PDSR] ; PIO pin state 1172 00000C0C E3110701 tst r1, #AT91_Spartan_init ; 1173 00000C10 0AFFFFFC beq spartan_hdr1 ; Wait for Spartan to be re ady 1174 00000C14 1175 00000C14 ; Want >5us delay before downloading. 1176 00000C14 ; Assumed to hide under serial comms. 1177 00000C14 1178 00000C14 ; Possibilities of failure? @@@ 1179 00000C14 1180 00000C14 EA000028 b FPGA_pkt_out ; 1181 00000C18 1182 00000C18 ; mov r0, #"A" ; 1183 00000C18 ; bl Host_out ; Signal success 1184 00000C18 ; b command_loop ; 1185 00000C18 1186 00000C18 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1187 00000C18 1188 00000C18 E59F08E8 ARM Macro Assembler Page 50 Virtex_header ldr r0, IO_PIO_base ; 1189 00000C1C 1190 00000C1C ; Force other PIO bits to correct state before resetting Virtex 1191 00000C1C E3A01802 mov r1, #AT91_Virtex_prog ; Reset Virtex 1192 00000C20 E5801034 str r1, [r0, #PIO_CODR] ; Programme pin low 1193 00000C24 1194 00000C24 E3A02008 mov r2, #8 ; Delay iterations 1195 00000C28 E2522001 virtex_hdr0 subs r2, r2, #1 ; Leave pin low for a while 1196 00000C2C 8AFFFFFD bhi virtex_hdr0 ; 1197 00000C30 1198 00000C30 E5801030 str r1, [r0, #PIO_SODR] ; Programme pin high again 1199 00000C34 1200 00000C34 E59F2014 ldr r2, Lit_EBI_base ; Set bus speed to no w ait states 1201 00000C38 E59F1014 ldr r1, Lit_EBI_fast_Virtex ; 1202 00000C3C E5821008 str r1, [r2, #EBI_CSR2] ; 1203 00000C40 1204 00000C40 E590103C virtex_hdr1 ldr r1, [r0, #PIO_PDSR] ; PIO pin state 1205 00000C44 E3110702 tst r1, #AT91_Virtex_init ; 1206 00000C48 0AFFFFFC beq virtex_hdr1 ; Wait for Virtex to be read y 1207 00000C4C 1208 00000C4C ; Possibilities of failure? @@@ 1209 00000C4C 1210 00000C4C EA00001A b FPGA_pkt_out ; 1211 00000C50 1212 00000C50 ; mov r0, #"A" ; 1213 00000C50 ; bl Host_out ; Signal success 1214 00000C50 ; b command_loop ; 1215 00000C50 1216 00000C50 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1217 00000C50 1218 00000C50 FFE00000 Lit_EBI_base DCD EBI_base 1219 00000C54 Lit_EBI_fast_Virtex 1220 00000C54 20003382 DCD (VIRTEX_base :AND: &FFF00000) :OR: CSEN :OR: BAT :OR: TDF1 :OR: Pg64M :OR: DBW8 1221 00000C58 Lit_EBI_slow_Virtex 1222 00000C58 200033A5 DCD (VIRTEX_base :AND: &FFF00000) :OR: CSEN :OR: BAT :OR: TDF1 :OR: Pg64M :OR: NWS2 :OR: DBW16 1223 00000C5C 1224 00000C5C ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1225 00000C5C ; R2 is local count (1..256) R3 points to global counter 1226 00000C5C ; Corrupts R0, R1, R4, R5, R6, R14 1227 00000C5C 1228 00000C5C E3A01202 Virtex_packet mov r1, #VIRTEX_base ; Virtex address ARM Macro Assembler Page 51 1229 00000C60 E3E05000 mov r5, #TRUE ; Virtex ID 1230 00000C64 IF Virtex_E 1231 00000C64 E3A06000 mov r6, #FALSE ; Don't reverse bytes when l oading 1232 00000C68 ELSE 1234 ENDIF 1235 00000C68 EA000002 b Spartan_pkt0 ; The rest is common 1236 00000C6C 1237 00000C6C E3A05000 Spartan_packet mov r5, #FALSE ; NOT Virtex ID 1238 00000C70 E3E06000 mov r6, #TRUE ; Reverse bytes before loadi ng 1239 00000C74 E3A01101 mov r1, #SPARTAN_base ; Spartan address 1240 00000C78 1241 00000C78 E5934000 Spartan_pkt0 ldr r4, [r3] ; 1242 00000C7C E1520004 cmp r2, r4 ; 1243 00000C80 8AFFFFCF bhi Dld_no_such_feature_pkt ; Waste characte rs and "Nack" 1244 00000C84 1245 00000C84 EB000261 Spartan_pkt1 bl Host_in ; Get byte 1246 00000C88 E3760001 cmp r6, #TRUE ; Should we flip byte? 1247 00000C8C 0B000222 bleq reverse_byte ; Correct for Xilinx No. sc heme 1248 00000C90 E5C10000 strb r0, [r1] ; Programme FPGA 1249 00000C94 1250 00000C94 E2444001 sub r4, r4, #1 ; Global count 1251 00000C98 E2522001 subs r2, r2, #1 ; Local count 1252 00000C9C 8AFFFFF8 bhi Spartan_pkt1 ; 1253 00000CA0 1254 00000CA0 E5834000 str r4, [r3] ; 1255 00000CA4 1256 00000CA4 E3540000 cmp r4, #0 ; Finished whole device? 1257 00000CA8 ; bne FPGA_pkt_out ; no 1258 00000CA8 ; cmp r5, #TRUE ; Am I the Virtex device? 1259 00000CA8 03750001 cmpeq r5, #TRUE ; or am I the Virtex device? 1260 00000CAC 1A000002 bne FPGA_pkt_out ; no 1261 00000CB0 ; Now finishing off Virtex ... 1262 00000CB0 E51F2068 ldr r2, Lit_EBI_base ; Set bus speed to some wait states 1263 00000CB4 E51F1064 ldr r1, Lit_EBI_slow_Virtex ; (currently two) 1264 00000CB8 E5821008 str r1, [r2, #EBI_CSR2] ; 1265 00000CBC 1266 00000CBC E3A00041 FPGA_pkt_out mov r0, #"A" ; Signal success 1267 00000CC0 EB000249 FPGA_pkt_outN bl Host_out ; Entry point if failure 1268 00000CC4 EAFFFEC0 b command_loop ; 1269 00000CC8 1270 00000CC8 ;------------------------------------------------------- ----------------------- ARM Macro Assembler Page 52 1271 00000CC8 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1272 00000CC8 ; Stop emulation 1273 00000CC8 1274 00000CC8 Proc_pause ; Suspend operation (same as "stop" ??) 1275 00000CC8 1276 00000CC8 E5D7000C Proc_stop ldrb r0, [r7, #arm_state - shared_variables] 1277 00000CCC E3100080 tst r0, #&80 ; Moving already? 1278 00000CD0 0AFFFEBD beq command_loop ; No - ignore 1279 00000CD4 1280 00000CD4 E5C7000D strb r0, [r7, #arm_state_old - shared_variabl es] 1281 00000CD8 E3A00040 mov r0, #State_stopped ; Set status to stop 1282 00000CDC E5C7000C strb r0, [r7, #arm_state - shared_variables] 1283 00000CE0 ; Signal to processor 1284 00000CE0 1285 00000CE0 EAFFFEB9 b command_loop ; 1286 00000CE4 1287 00000CE4 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1288 00000CE4 ; Continue as before stopped - same breakpoint (etc.) en ables, same number of steps 1289 00000CE4 ; Step if was stepping, run if was running 1290 00000CE4 1291 00000CE4 E5D7000C Proc_continue ldrb r0, [r7, #arm_state - shared_variables] 1292 00000CE8 1293 00000CE8 E20020C0 and r2, r0, #&C0 ; Reset, stopped, running, stepping? 1294 00000CEC E3520040 cmp r2, #&40 ; In a "stopped" state? 1295 00000CF0 1AFFFEB5 bne command_loop ; No - do nothing 1296 00000CF4 1297 00000CF4 E3500043 cmp r0, #State_count_out ; States from which there is no 1298 00000CF8 13500041 cmpne r0, #State_stop_req ; sensible way to ` continue' 1299 00000CFC 0AFFFEB2 beq command_loop ; 1300 00000D00 1301 00000D00 E5D7000D ldrb r0, [r7, #arm_state_old - shared_variabl es] 1302 00000D04 E20020C0 and r2, r0, #&C0 ; 1303 00000D08 E35200C0 cmp r2, #&C0 ; Was stepping? 1304 00000D0C 1305 00000D0C 05972014 ldreq r2, [r7, #arm_step_count - shared_variab les] 1306 00000D10 01120002 tsteq r2, r2 ; Steps = 0, regardless? 1307 00000D14 15C7000C strneb r0, [r7, #arm_state - shared_variables] 1308 00000D18 ; New state if wasn't stepping OR step_count non-zero 1309 00000D18 1310 00000D18 EAFFFEAB b command_loop ; 1311 00000D1C 1312 00000D1C E597102C Proc_set_flags ldr r1, [r7, #Running_flags - shared_variabl es] ARM Macro Assembler Page 53 1313 00000D20 E3C11C03 bic r1, r1, #Run_I_bit :OR: Run_F_bit 1314 00000D24 EB000239 bl Host_in ; 1315 00000D28 E3100002 tst r0, #&02 ; 1316 00000D2C 13811C02 orrne r1, r1, #Run_I_bit ; 1317 00000D30 E3100001 tst r0, #&01 ; 1318 00000D34 13811C01 orrne r1, r1, #Run_F_bit ; 1319 00000D38 E587102C str r1, [r7, #Running_flags - shared_variabl es] 1320 00000D3C EAFFFEA2 b command_loop ; 1321 00000D40 1322 00000D40 E3A00000 Proc_get_flags mov r0, #0 ; 1323 00000D44 E597102C ldr r1, [r7, #Running_flags - shared_variabl es] 1324 00000D48 E3110C02 tst r1, #Run_I_bit ; 1325 00000D4C 13800002 orrne r0, r0, #&02 ; 1326 00000D50 E3110C01 tst r1, #Run_F_bit ; 1327 00000D54 13800001 orrne r0, r0, #&01 ; 1328 00000D58 EB000223 bl Host_out ; 1329 00000D5C EAFFFE9A b command_loop ; 1330 00000D60 1331 00000D60 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1332 00000D60 ; What is emulator doing now? 1333 00000D60 1334 00000D60 E5D7100C Proc_status ldrb r1, [r7, #arm_state - shared_variables] 1335 00000D64 1336 00000D64 E1A00321 mov r0, r1, lsr #6 ; Basic status class 1337 00000D68 E28F2038 adr r2, status_table ; 1338 00000D6C E0822100 add r2, r2, r0, lsl #2 ; 4 byte entries 1339 00000D70 1340 00000D70 E201103F and r1, r1, #&3F ; 1341 00000D74 E5D20001 ldrb r0, [r2, #1] ; Sub-table size 1342 00000D78 E1510000 cmp r1, r0 ; Entry in subtable? 1343 00000D7C 25D20000 ldrhsb r0, [r2] ; no - get default 1344 00000D80 2A000002 bhs Proc_status1 ; 1345 00000D84 1346 00000D84 E5D20002 ldrb r0, [r2, #2] ; 1347 00000D88 E08F0000 2 add r0, pc, r0 ; R0 is offset from here to sub_table 1348 00000D8C E7D00001 ldrb r0, [r0, r1] ; 1349 00000D90 1350 00000D90 1351 00000D90 EB000215 Proc_status1 bl Host_out ; Output host status 1352 00000D94 1353 00000D94 E5970014 ldr r0, [r7, #arm_step_count - shared_variab les] 1354 00000D98 EB0001FF bl Host_put_word ; Number of steps remaining 1355 00000D9C 1356 00000D9C E5970018 ldr r0, [r7, #arm_instr_count - shared_varia bles] 1357 00000DA0 EB0001FD bl Host_put_word ARM Macro Assembler Page 54 ; Instructions since reset 1358 00000DA4 1359 00000DA4 EAFFFE88 b command_loop ; 1360 00000DA8 1361 00000DA8 00 00 00 00 status_table DCB &00, 0, 0, 0 ; Reset states 1362 00000DAC 40 04 DCB &40, %f21-%f20 ; Reset states 1363 00000DAE 28 00 DCB %f20-(%b2+8), 0 ; 1364 00000DB0 80 06 DCB &80, %f31-%f30 ; Running states 1365 00000DB2 2C 00 DCB %f30-(%b2+8), 0 ; 1366 00000DB4 80 00 00 00 DCB &80, 0, 0, 0 ; Stepping states 1367 00000DB8 1368 00000DB8 ; Cross reference #A# 1369 00000DB8 20 1370 00000DB8 40 DCB &40 ; State_stopped 1371 00000DB9 44 DCB &44 ; State_stop_req 1372 00000DBA 41 DCB &41 ; State_stop_bkpt 1373 00000DBB 40 DCB &40 ; State_count_out 1374 00000DBC 21 1375 00000DBC 1376 00000DBC 30 1377 00000DBC 80 DCB &80 ; State_running 1378 00000DBD 80 DCB &80 ; State_running_BL 1379 00000DBE 81 DCB &81 ; State_running_SWI 1380 00000DBF 80 DCB &80 ; State_running_IRQ 1381 00000DC0 80 DCB &80 ; State_running_FIQ 1382 00000DC1 80 DCB &80 ; State_running_abt 1383 00000DC2 31 1384 00000DC2 00 00 ALIGN 1385 00000DC4 1386 00000DC4 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1387 00000DC4 1388 00000DC4 E2015007 Get_reg and r5, r1, #7 ; Size 1389 00000DC8 E1A04002 mov r4, r2 ; Save address 1390 00000DCC 1391 00000DCC E1A01004 Get_reg1 mov r1, r4 ; Register address 1392 00000DD0 EB00005C bl G_reg ; Translate & read 1393 00000DD4 E28FE018 adr lr, Get_reg2 ; Save return address 1394 00000DD8 E3A01000 mov r1, #0 ; In case of double ... 1395 00000DDC ; r5 not range checked @@@ 1396 00000DDC E79F2105 ldr r2, [pc, r5, lsl #2] ; R5 (size) must be preserved 1397 00000DE0 E08FF002 add pc, pc, r2 ; R2 already trashed by G_re g 1398 00000DE4 1399 00000DE4 00000804 DCD Host_out - %f1 ; 1400 00000DE8 1 1401 00000DE8 000007A8 DCD Host_put_halfword - %b1 ; 1402 00000DEC 000007B4 DCD Host_put_word - %b1 ; 1403 00000DF0 0000076C DCD Host_put_double - %b1 ; 1404 00000DF4 1405 00000DF4 E2844001 Get_reg2 ARM Macro Assembler Page 55 add r4, r4, #1 ; Next register 1406 00000DF8 E2533001 subs r3, r3, #1 ; 1407 00000DFC 1AFFFFF2 bne Get_reg1 ; 1408 00000E00 1409 00000E00 EAFFFE71 b command_loop ; 1410 00000E04 1411 00000E04 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1412 00000E04 ; Register addresses are bytes (quite wrongly!) 1413 00000E04 1414 00000E04 E2015007 Put_reg and r5, r1, #7 ; Size 1415 00000E08 E1A04002 mov r4, r2 ; Save address 1416 00000E0C 1417 00000E0C E28FE014 Put_reg1 adr lr, Put_reg2 ; Save return address 1418 00000E10 ; r5 not range checked @@@ 1419 00000E10 E79F2105 ldr r2, [pc, r5, lsl #2] ; Preserve R5 (size) 1420 00000E14 E08FF002 add pc, pc, r2 ; R2 scratched in P_reg 1421 00000E18 1422 00000E18 000007F4 DCD Host_in - %f1 ; 1423 00000E1C 1 1424 00000E1C 0000079C DCD Host_get_halfword - %b1 ; 1425 00000E20 0000074C DCD Host_get_word - %b1 ; 1426 00000E24 0000071C DCD Host_get_double - %b1 ; 1427 00000E28 1428 00000E28 E1A01004 Put_reg2 mov r1, r4 ; 1429 00000E2C EB000050 bl P_reg ; Write back 1430 00000E30 E2844001 add r4, r4, #1 ; 1431 00000E34 E2533001 subs r3, r3, #1 ; 1432 00000E38 1AFFFFF3 bne Put_reg1 ; 1433 00000E3C 1434 00000E3C EAFFFE62 b command_loop ; 1435 00000E40 1436 00000E40 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1437 00000E40 1438 00000E40 E2011007 Get_mem and r1, r1, #7 ; 1439 00000E44 E3510004 cmp r1, #(%f11 - %f10) ; Only four defined sizes 1440 00000E48 2AFFFE5F bhs command_loop ; 1441 00000E4C 1442 00000E4C E7DF0001 ldrb r0, [pc, r1] ; Load byte offset 1443 00000E50 E08FF100 add pc, pc, r0, lsl #2 ; Multiply offset by four 1444 00000E54 1445 00000E54 10 1446 00000E54 00 DCB (Get_mem_b - %f1) / 4 ; 0 1447 00000E55 07 DCB (Get_mem_h - %f1) / 4 ; 1 1448 00000E56 0E DCB (Get_mem_w - %f1) / 4 ; 2 1449 00000E57 15 DCB (Get_mem_d - %f1) / 4 ; 3 1450 00000E58 1 1451 00000E58 11 1452 00000E58 ALIGN ARM Macro Assembler Page 56 1453 00000E58 1454 00000E58 1455 00000E58 EB0000A7 Get_mem_b bl read_memory_b ; Read byte 1456 00000E5C E1A00001 mov r0, r1 ; 1457 00000E60 E2822001 add r2, r2, #1 ; Increment address 1458 00000E64 EB0001E0 bl Host_out ; Output byte 1459 00000E68 E2533001 subs r3, r3, #1 ; Decrement count 1460 00000E6C 1AFFFFF9 bne Get_mem_b ; and repeat as required 1461 00000E70 1462 00000E70 EAFFFE55 b command_loop ; 1463 00000E74 1464 00000E74 1465 00000E74 EB000090 Get_mem_h bl read_memory_h ; 1466 00000E78 E1A00001 mov r0, r1 ; 1467 00000E7C E2822002 add r2, r2, #2 ; 1468 00000E80 EB0001C2 bl Host_put_halfword ; 1469 00000E84 E2533001 subs r3, r3, #1 ; 1470 00000E88 1AFFFFF9 bne Get_mem_h ; 1471 00000E8C 1472 00000E8C EAFFFE4E b command_loop ; 1473 00000E90 1474 00000E90 1475 00000E90 EB000080 Get_mem_w bl read_memory_w ; 1476 00000E94 E1A00001 mov r0, r1 ; 1477 00000E98 E2822004 add r2, r2, #4 ; 1478 00000E9C EB0001BE bl Host_put_word ; 1479 00000EA0 E2533001 subs r3, r3, #1 ; 1480 00000EA4 1AFFFFF9 bne Get_mem_w ; 1481 00000EA8 1482 00000EA8 EAFFFE47 b command_loop ; 1483 00000EAC 1484 00000EAC 1485 00000EAC EB00006E Get_mem_d bl read_memory_d ; R0:R1 := [R2] 1486 00000EB0 E1A0E000 mov r14, r0 ; R14 is scratch here 1487 00000EB4 E1A00001 mov r0, r1 ; Swap R1, R0 1488 00000EB8 E1A0100E mov r1, r14 ; 1489 00000EBC E2822008 add r2, r2, #8 ; 1490 00000EC0 EB0001A3 bl Host_put_double ; 1491 00000EC4 E2533001 subs r3, r3, #1 ; 1492 00000EC8 1AFFFFF7 bne Get_mem_d ; 1493 00000ECC 1494 00000ECC EAFFFE3E b command_loop ; 1495 00000ED0 1496 00000ED0 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1497 00000ED0 1498 00000ED0 E2011007 Put_mem and r1, r1, #7 ; 1499 00000ED4 E3510004 cmp r1, #(%f11 - %f10) ; Only four defined sizes 1500 00000ED8 2AFFFE3B bhs command_loop ; ARM Macro Assembler Page 57 1501 00000EDC 1502 00000EDC 1503 00000EDC ;Proposed replacement - shorter by 7 words ... **NEW C ODE** @@@ 1504 00000EDC ; adr r14, Put_mem_table ; 1505 00000EDC ; add r14, r14, r1, lsl #2 ; Could shrink table (?) 1506 00000EDC ; ldrsh r5, [r14] ; Offset to serial input routine 1507 00000EDC ; ldrsh r6, [r14, #4] ; Offset to memory output routin e 1508 00000EDC ;3 add r5, pc, r5 ; Address of serial input routine 1509 00000EDC ;4 add r6, pc, r6 ; Address of memory output routine 1510 00000EDC ; mov r4, #1 ; 1511 00000EDC ; mov r4, r4, lsr r1 ; Transfer size (address incremen t) 1512 00000EDC ; 1513 00000EDC ;Put_mem_all adr lr, %f1 ; 1514 00000EDC ; bx r5 ; Get element 1515 00000EDC ;1 adr lr, %f2 ; 1516 00000EDC ; bx r6 ; Store element 1517 00000EDC ;2 add r2, r2, r4 ; Step address 1518 00000EDC ; subs r3, r3, #1 ; 1519 00000EDC ; bne Put_mem_all ; 1520 00000EDC ; 1521 00000EDC ; b command_loop ; 1522 00000EDC ; 1523 00000EDC ;Put_mem_table DCW Host_in - %b3 - 8, write_me mory_b - %b4 - 8 1524 00000EDC ; DCW Host_get_halfword - %b3 - 8, write_memory_h - %b4 - 8 1525 00000EDC ; DCW Host_get_word - %b3 - 8, write_memory_w - %b4 - 8 1526 00000EDC ; DCW Host_get_double - %b3 - 8, write_memory_d - %b4 - 8 1527 00000EDC ; 1528 00000EDC ; ALIGN 1529 00000EDC 1530 00000EDC E7DF0001 ldrb r0, [pc, r1] ; Load byte offset 1531 00000EE0 E08FF100 add pc, pc, r0, lsl #2 ; Multiply offset by four 1532 00000EE4 1533 00000EE4 10 1534 00000EE4 00 DCB (Put_mem_b - %f1) / 4 ; 0 1535 00000EE5 06 DCB (Put_mem_h - %f1) / 4 ; 1 1536 00000EE6 0C DCB (Put_mem_w - %f1) / 4 ; 2 1537 00000EE7 12 DCB (Put_mem_d - %f1) / 4 ; 3 1538 00000EE8 1 1539 00000EE8 11 1540 00000EE8 ALIGN 1541 00000EE8 1542 00000EE8 EB0001C8 Put_mem_b bl Host_in ; 1543 00000EEC EB00011B bl write_memory_b ; 1544 00000EF0 E2822001 add r2, r2, #1 ; 1545 00000EF4 E2533001 subs r3, r3, #1 ; 1546 00000EF8 1AFFFFFA bne Put_mem_b ; 1547 00000EFC 1548 00000EFC EAFFFE32 b command_loop ; 1549 00000F00 ARM Macro Assembler Page 58 1550 00000F00 1551 00000F00 EB0001AC Put_mem_h bl Host_get_halfword ; 1552 00000F04 EB000104 bl write_memory_h ; 1553 00000F08 E2822002 add r2, r2, #2 ; 1554 00000F0C E2533001 subs r3, r3, #1 ; 1555 00000F10 1AFFFFFA bne Put_mem_h ; 1556 00000F14 1557 00000F14 EAFFFE2C b command_loop ; 1558 00000F18 1559 00000F18 1560 00000F18 EB000192 Put_mem_w bl Host_get_word ; 1561 00000F1C EB0000F4 bl write_memory_w ; 1562 00000F20 E2822004 add r2, r2, #4 ; 1563 00000F24 E2533001 subs r3, r3, #1 ; 1564 00000F28 1AFFFFFA bne Put_mem_w ; 1565 00000F2C 1566 00000F2C EAFFFE26 b command_loop ; 1567 00000F30 1568 00000F30 EB000180 Put_mem_d bl Host_get_double ; 1569 00000F34 EB0000E2 bl write_memory_d ; 1570 00000F38 E2822008 add r2, r2, #8 ; 1571 00000F3C E2533001 subs r3, r3, #1 ; 1572 00000F40 1AFFFFFA bne Put_mem_d ; 1573 00000F44 1574 00000F44 EAFFFE20 b command_loop ; 1575 00000F48 1576 00000F48 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1577 00000F48 ; Pass register ID in R1, return value in R0 1578 00000F48 ; Corrupts R2 1579 00000F48 1580 00000F48 E35100D1 G_reg cmp r1, #&D1 ; Decodes to SPSR_fiq 1581 00000F4C 83A00000 movhi r0, #0 ; Register out of range 1582 00000F50 81A0F00E movhi pc, lr ; so return zero 1583 00000F54 1584 00000F54 E201201F and r2, r1, #&1F ; Register number only 1585 00000F58 E3520011 cmp r2, #&11 ; Above legal range? 1586 00000F5C 83A00000 movhi r0, #0 ; If so return zero 1587 00000F60 81A0F00E movhi pc, lr ; and return 1588 00000F64 1589 00000F64 E92D4230 stmfd sp!, {r4-r5, r9, lr} ; Else do some work 1590 00000F68 EB000014 bl Find_reg ; 1591 00000F6C E7990102 ldr r0, [r9, r2, lsl #2] ; Get register 1592 00000F70 E8BD8230 ldmfd sp!, {r4-r5, r9, pc} ; and return 1593 00000F74 1594 00000F74 1595 00000F74 E35100D1 P_reg cmp r1, #&D1 ; Decodes to SPSR_fiq 1596 00000F78 81A0F00E movhi pc, lr ; So just return 1597 00000F7C 1598 00000F7C E201201F and r2, r1, #&1F ; Register number only ARM Macro Assembler Page 59 1599 00000F80 E3520011 cmp r2, #&11 ; Above legal range? 1600 00000F84 81A0F00E movhi pc, lr ; Just return 1601 00000F88 1602 00000F88 E3520010 cmp r2, #&10 ; CPSR 1603 00000F8C 0A000003 beq P_reg_CPSR ; 1604 00000F90 1605 00000F90 E92D4230 stmfd sp!, {r4-r5, r9, lr} ; Else do some work 1606 00000F94 EB000009 bl Find_reg ; 1607 00000F98 E7890102 str r0, [r9, r2, lsl #2] ; Put register 1608 00000F9C E8BD8230 ldmfd sp!, {r4-r5, r9, pc} ; and return 1609 00000FA0 1610 00000FA0 1611 00000FA0 E92D427F P_reg_CPSR stmfd sp!, {r0-r6, r9, lr} ; 1612 00000FA4 E597901C ldr r9, [r7, #reg_area_ptr - shared_variable s] 1613 00000FA8 ; Find register block 1614 00000FA8 E200100F and r1, r0, #&F ; New mode 1615 00000FAC E59930A8 ldr r3, [r9, #sim_CPSR - reg_block] ; Old CPSR 1616 00000FB0 E58900A8 str r0, [r9, #sim_CPSR - reg_block] ; Save new CPSR 1617 00000FB4 E203000F and r0, r3, #&F ; Old mode 1618 00000FB8 EB000462 bl mode_reg_swap ; Corrupts R0-R6 1619 00000FBC E8BD827F ldmfd sp!, {r0-r6, r9, pc} ; 1620 00000FC0 1621 00000FC0 ; Pass (legal) register ID in R1 and (R1 AND 1F) in R2 1622 00000FC0 ; Return offset (/4) in R2, area in R9 1623 00000FC0 ; Corrupts: R4-R5 1624 00000FC0 ; Register ID is 3 bits mode {current, user/sys, svc, ab t, undef, IRQ, FIQ, ???} 1625 00000FC0 ; and 5 bits register address (10=CPSR, 11=SPSR, 12+ no t defined) 1626 00000FC0 1627 00000FC0 E597901C Find_reg ldr r9, [r7, #reg_area_ptr - shared_variable s] 1628 00000FC4 ; Find register block 1629 00000FC4 1630 00000FC4 ; and r2, r1, #&1F ; Register number only 1631 00000FC4 E3520008 cmp r2, #&08 ; R0..R7? 1632 00000FC8 31A0F00E movlo pc, lr ; return 1633 00000FCC 1634 00000FCC E352000F cmp r2, #15 ; PC? 1635 00000FD0 03A0202B moveq r2, #(sim_PC - reg_block)/4 ; PC offset 1636 00000FD4 01A0F00E moveq pc, lr ; 1637 00000FD8 1638 00000FD8 E3520010 cmp r2, #&10 ; CPSR? 1639 00000FDC 03A0202A moveq r2, #(sim_CPSR - reg_block)/4 ; CPSR offset 1640 00000FE0 01A0F00E moveq pc, lr ; 1641 00000FE4 ; Unbanked registers now dealt with 1642 00000FE4 1643 00000FE4 E59950A8 ldr r5, [r9, #sim_CPSR - reg_block] ; Load CPSR to R5 1644 00000FE8 E205500F and r5, r5, #&F ; Mask out mode (32-bit only ARM Macro Assembler Page 60 ) 1645 00000FEC E28F4058 adr r4, mode_tab ; Translation table 1646 00000FF0 E7D45005 ldrb r5, [r4, r5] ; Get `internal' mode encod ing 1647 00000FF4 1648 00000FF4 E3520011 cmp r2, #&11 ; SPSR? 1649 00000FF8 0A00000E beq Find_reg_SPSR ; 1650 00000FFC 1651 00000FFC E1B042A1 movs r4, r1, lsr #5 ; Mode as passed in (0=cu rrent) 1652 00001000 11550004 cmpne r5, r4 ; Specified mode is current anyway? 1653 00001004 01A0F00E moveq pc, lr ; Then just return 1654 00001008 1655 00001008 E352000D cmp r2, #13 ; Now in a background reg. s et 1656 0000100C 2A000005 bhs Find_reg1 ; R13, R14 1657 00001010 1658 00001010 E3550006 cmp r5, #6 ; Running in FIQ mode? 1659 00001014 02822007 addeq r2, r2, #(sim_R8_user - sim_R8)/4 ; Yes - use user offset 1660 00001018 01A0F00E moveq pc, lr ; and return (modes can't m atch) 1661 0000101C E3540006 cmp r4, #6 ; Asked for FIQ mode? 1662 00001020 02822016 addeq r2, r2, #(sim_R8_FIQ - sim_R8)/4 ; Yes, use FIQ offset 1663 00001024 E1A0F00E mov pc, lr ; else default to current ba nk 1664 00001028 1665 00001028 E28F502C Find_reg1 adr r5, R13_offset_table ; Banked R13, R14 1666 0000102C E7D55004 ldrb r5, [r5, r4] ; Get extra R13 offset for mode 1667 00001030 E0822005 add r2, r2, r5 ; add offset to register num ber 1668 00001034 E1A0F00E mov pc, lr ; and return 1669 00001038 1670 00001038 E31100E0 Find_reg_SPSR tst r1, #&E0 ; Requested specific mode? 1671 0000103C 11A052A1 movne r5, r1, lsr #5 ; Overridden by request 1672 00001040 1673 00001040 E28F401B adr r4, SPSR_offset_table ; SPSR positions 1674 00001044 E7D42005 ldrb r2, [r4, r5] ; Get SPSR offset for mode 1675 00001048 E1A0F00E mov pc, lr ; and return 1676 0000104C 1677 0000104C 1678 0000104C ; Translation table to internal mode numbers (0=current) 1679 0000104C 1680 0000104C 01 06 05 02 mode_tab DCB 1, 6, 5, 2 ; User, FIQ, IRQ, Supervisor 1681 00001050 00 00 00 03 DCB 0, 0, 0, 3 ; 3* Not defined, Abort 1682 00001054 00 00 00 04 DCB 0, 0, 0, 4 ; 3* Not defined, Undefined ARM Macro Assembler Page 61 1683 00001058 00 00 00 01 DCB 0, 0, 0, 1 ; 3* Not defined, System 1684 0000105C 1685 0000105C R13_offset_table ; For finding SP, LR for par ticular mode 1686 0000105C 00 DCB 0 1687 0000105D 07 DCB (sim_R13_user - sim_R13) / 4 1688 0000105E 09 DCB (sim_R13_svc - sim_R13) / 4 1689 0000105F 0B DCB (sim_R13_abt - sim_R13) / 4 1690 00001060 0D DCB (sim_R13_undef - sim_R13) / 4 1691 00001061 0F DCB (sim_R13_IRQ - sim_R13) / 4 1692 00001062 16 DCB (sim_R13_FIQ - sim_R13) / 4 1693 00001063 1694 00001063 SPSR_offset_table ; For finding SPSR for parti cular mode 1695 00001063 00 DCB 0 1696 00001064 2A DCB (sim_CPSR - reg_block)/4 1697 00001065 25 DCB (sim_SPSR_svc - reg_block)/4 1698 00001066 26 DCB (sim_SPSR_abt - reg_block)/4 1699 00001067 27 DCB (sim_SPSR_undef - reg_block)/4 1700 00001068 28 DCB (sim_SPSR_irq - reg_block)/4 1701 00001069 29 DCB (sim_SPSR_fiq - reg_block)/4 1702 0000106A 1703 0000106A 00 00 ALIGN 1704 0000106C 1705 0000106C ;------------------------------------------------------- ----------------------- 1706 0000106C ; Address in R2, data returned in R0:R1 (R0 is more sign ificant!) 1707 0000106C 1708 0000106C E5971020 read_memory_d ldr r1, [r7, #mem_area_start - shared_variab les] ; 1709 00001070 E1520001 cmp r2, r1 ; 1710 00001074 3A000030 blo read_memory_IO_D ; Address too low 1711 00001078 E5971024 ldr r1, [r7, #mem_area_end - shared_variable s] 1712 0000107C E1520001 cmp r2, r1 ; 1713 00001080 2A00002D bhs read_memory_IO_D ; Address too high 1714 00001084 1715 00001084 E5971028 ldr r1, [r7, #mem_area_pos - shared_variable s] 1716 00001088 E2810004 add r0, r1, #4 ; Address in range 1717 0000108C E7921001 ldr r1, [r2, r1] ; 1718 00001090 E7920000 ldr r0, [r2, r0] ; Next word 1719 00001094 E1A0F00E mov pc, lr ; 1720 00001098 1721 00001098 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1722 00001098 ; Address in R2, data returned in R1 1723 00001098 1724 00001098 E5971020 read_memory_w ldr r1, [r7, #mem_area_start - shared_variab les] ; 1725 0000109C E1520001 cmp r2, r1 ; ARM Macro Assembler Page 62 1726 000010A0 3A00002C blo read_memory_IO_W ; Address too low 1727 000010A4 E5971024 ldr r1, [r7, #mem_area_end - shared_variable s] 1728 000010A8 E1520001 cmp r2, r1 ; 1729 000010AC 2A000029 bhs read_memory_IO_W ; Address too high 1730 000010B0 1731 000010B0 E5971028 ldr r1, [r7, #mem_area_pos - shared_variable s] 1732 000010B4 E7921001 ldr r1, [r2, r1] ; Address in range 1733 000010B8 E1A0F00E mov pc, lr ; 1734 000010BC 1735 000010BC ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1736 000010BC ; Address in R2, data returned in R1 1737 000010BC 1738 000010BC E5971020 read_memory_h ldr r1, [r7, #mem_area_start - shared_variab les] ; 1739 000010C0 E1520001 cmp r2, r1 ; 1740 000010C4 3A000005 blo read_memory_h1 ; Address too low 1741 000010C8 E5971024 ldr r1, [r7, #mem_area_end - shared_variable s] 1742 000010CC E1520001 cmp r2, r1 ; 1743 000010D0 2A000002 bhs read_memory_h1 ; Address too high 1744 000010D4 1745 000010D4 E5971028 ldr r1, [r7, #mem_area_pos - shared_variable s] 1746 000010D8 E19210B1 ldrh r1, [r2, r1] ; Address in range 1747 000010DC E1A0F00E mov pc, lr ; 1748 000010E0 1749 000010E0 read_memory_h1 1750 000010E0 E202120F and r1, r2, #&F0000000 ; Bodgery! @@ 1751 000010E4 E3510203 cmp r1, #Virtex_page ; Virtex? 1752 000010E8 1A000021 bne read_memory_IO_H ; Not Virtex 1753 000010EC 1754 000010EC E3C2120F bic r1, r2, #&F0000000 ; Find page offset 1755 000010F0 E3811202 orr r1, r1, #VIRTEX_base ; Find true address 1756 000010F4 E5D11000 ldrb r1, [r1] ; 1757 000010F8 E1A0F00E mov pc, lr ; 1758 000010FC 1759 000010FC ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1760 000010FC ; Address in R2, data returned in R1 1761 000010FC 1762 000010FC E5971020 read_memory_b ldr r1, [r7, #mem_area_start - shared_variab les] ; 1763 00001100 E1520001 cmp r2, r1 ; 1764 00001104 3A000005 blo read_memory_b1 ; Address too low 1765 00001108 E5971024 ldr r1, [r7, #mem_area_end - shared_variable s] 1766 0000110C E1520001 cmp r2, r1 ; 1767 00001110 2A000002 bhs read_memory_b1 ; Address too high 1768 00001114 ARM Macro Assembler Page 63 1769 00001114 E5971028 ldr r1, [r7, #mem_area_pos - shared_variable s] 1770 00001118 E7D21001 ldrb r1, [r2, r1] ; Address in range 1771 0000111C E1A0F00E mov pc, lr ; 1772 00001120 1773 00001120 1774 00001120 read_memory_b1 1775 00001120 E202120F and r1, r2, #&F0000000 ; Bodgery! @@ 1776 00001124 E3510202 cmp r1, #Spartan_page ; Spartan? 1777 00001128 1A000015 bne read_memory_IO_B ; Not Spartan 1778 0000112C 1779 0000112C E3C2120F bic r1, r2, #&F0000000 ; Find page offset 1780 00001130 E3811101 orr r1, r1, #SPARTAN_base ; Find true address 1781 00001134 E5D11000 ldrb r1, [r1] ; 1782 00001138 E1A0F00E mov pc, lr ; 1783 0000113C 1784 0000113C ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1785 0000113C 1786 0000113C E92D4004 read_memory_IO_D stmfd sp!, {r2,lr} ; Fetch word (& align) 1787 00001140 EB000004 bl read_memory_IO_W ; Fetch double word 1788 00001144 E92D0002 stmfd sp!, {r1} ; Save low word 1789 00001148 E2822004 add r2, r2, #4 ; 1790 0000114C EB000001 bl read_memory_IO_W ; Fetch double word 1791 00001150 E1A00001 mov r0, r1 ; High word 1792 00001154 E8BD8006 ldmfd sp!, {r1,r2,pc} ; Restore all and return 1793 00001158 1794 00001158 E92D4005 read_memory_IO_W stmfd sp!, {r0,r2,lr} ; Fetch word (& align) 1795 0000115C E2020003 and r0, r2, #3 ; Byte position 1796 00001160 E3C22003 bic r2, r2, #3 ; 1797 00001164 read_memory_IO_W_1 1798 00001164 EB000006 bl read_memory_IO_B ; Get byte 1799 00001168 E1A00180 mov r0, r0, lsl #3 ; 8 * byte position 1800 0000116C E1A01071 mov r1, r1, ror r0 ; Fix up word 1801 00001170 E8BD8005 ldmfd sp!, {r0,r2,pc} ; Restore and return 1802 00001174 1803 00001174 E92D4005 read_memory_IO_H stmfd sp!, {r0,r2,lr} ; Fetch halfword 1804 00001178 E2020001 and r0, r2, #1 ; Byte position 1805 0000117C E3C22001 bic r2, r2, #1 ; 1806 00001180 EAFFFFF7 b read_memory_IO_W_1 ; Same from here 1807 00001184 1808 00001184 1809 00001184 E3520201 read_memory_IO_B cmp r2, #IO_area_start ; Get I/O byte (byte #0s only) 1810 00001188 3A00000C blo read_memory_abort ; Address too low 1811 0000118C E3520202 cmp r2, #IO_area_end ; 1812 00001190 2A00000A bhs read_memory_abort ; Address too high 1813 00001194 1814 00001194 E3120003 tst r2, #3 ; ARM Macro Assembler Page 64 1815 00001198 13A01000 movne r1, #0 ; Return 0 unless byte #0 1816 0000119C 11A0F00E movne pc, lr ; 1817 000011A0 1818 000011A0 E92D4001 stmfd sp!, {r0, lr} ; 1819 000011A4 E202003C and r0, r2, #&3C ; Partial decode 1820 000011A8 1821 000011A8 E7DF0120 ldrb r0, [pc, r0, lsr #2] ; Get offset 1822 000011AC E08FF100 add pc, pc, r0, lsl #2 ; Multiply `offset' by 4 1823 000011B0 1824 000011B0 ; Relocatable jump table to different devices 1825 000011B0 0B DCB (Rd_IO_portA - %f1) / 4 ; 00 1826 000011B1 0F DCB (Rd_IO_portB - %f1) / 4 ; 04 1827 000011B2 08 DCB (Rd_IO_timer - %f1) / 4 ; 08 1828 000011B3 3E DCB (Rd_IO_timer_cmp-%f1)/4 ; 0C 1829 000011B4 1 ; One word into table 1830 000011B4 1D DCB (Rd_IO_RxD - %b1) / 4 ; 10 1831 000011B5 2C DCB (Rd_IO_serial_status - %b1) / 4 ; 14 1832 000011B6 3A DCB (Rd_IO_irq - %b1) / 4 ; 18 1833 000011B7 3C DCB (Rd_IO_ien - %b1) / 4 ; 1C 1834 000011B8 40 DCB (Rd_serial_No- %b1) / 4 ; 20 (R2 still holds addr.) 1835 000011B9 40 DCB (Rd_serial_No- %b1) / 4 ; 24 1836 000011BA 40 DCB (Rd_serial_No- %b1) / 4 ; 28 1837 000011BB 40 DCB (Rd_serial_No- %b1) / 4 ; 2C 1838 000011BC 38 DCB (Rd_IO_none - %b1) / 4 ; 30 Reserved 1839 000011BD 38 DCB (Rd_IO_none - %b1) / 4 ; 34 1840 000011BE 38 DCB (Rd_IO_none - %b1) / 4 ; 38 1841 000011BF 38 DCB (Rd_IO_none - %b1) / 4 ; 3C 1842 000011C0 1843 000011C0 1844 000011C0 read_memory_abort 1845 000011C0 E202120F and r1, r2, #&F0000000 ; Hack to read Ethernet chip 1846 000011C4 E3510203 cmp r1, #ETHERNET_base 1847 000011C8 13A01000 movne r1, #0 ; "Abort", for now @@@ 1848 000011CC 01D210B0 ldreqh r1, [r2] ; 1849 000011D0 1850 000011D0 ; mov r1, #0 ; "Abort", for now @@@ 1851 000011D0 E1A0F00E mov pc, lr ; 1852 000011D4 1853 000011D4 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1854 000011D4 ; Input ports 1855 000011D4 1856 000011D4 E3A00040 Rd_IO_timer mov r0, #Line_time_clk - Mon_RAM_start 1857 000011D8 E5D01000 Rd_IO_out ldrb r1, [r0] ; General byte-read exit poi nt 1858 000011DC E8BD8001 ldmfd sp!, {r0, pc} ; used to save space 1859 000011E0 1860 000011E0 1861 000011E0 ; Read the bottom eight AT91 PIO lines 1862 000011E0 E59F0320 Rd_IO_portA ARM Macro Assembler Page 65 ldr r0, IO_PIO_base ; 1863 000011E4 E590003C ldr r0, [r0, #PIO_PDSR] ; Pin state 1864 000011E8 E20010FF and r1, r0, #&FF ; Eight bits only 1865 000011EC E8BD8001 ldmfd sp!, {r0, pc} ; 1866 000011F0 1867 000011F0 1868 000011F0 ; Read another selection of AT91 PIO lines 1869 000011F0 E92D0008 Rd_IO_portB stmfd sp!, {r3} ; Need more space 1870 000011F4 E59F030C ldr r0, IO_PIO_base ; 1871 000011F8 E590003C ldr r0, [r0, #PIO_PDSR] ; Pin state 1872 000011FC ; ldr r1, IO_PIO_portB ; 1873 000011FC ; and r0, r0, r1 ; Relevant bits only 1874 000011FC E59F130C ldr r1, IO_PIO_portB_inv ; 1875 00001200 E0200001 eor r0, r0, r1 ; Invert some bits 1876 00001204 1877 00001204 E28FEFC2 adr r14, IO_PIO_portB_tab ; Bit positions 1878 00001208 E3A01401 mov r1, #&01000000 ; Counter & Accumulator 1879 0000120C 1880 0000120C E4DE3001 Rd_IO_portB_lp ldrb r3, [r14], #1 ; Find next bit position 1881 00001210 E2833001 add r3, r3, #1 ; Shift down to carry 1882 00001214 E1100330 tst r0, r0, lsr r3 ; Set carry to bit value 1883 00001218 E0B11001 adcs r1, r1, r1 ; Shift into accumulator 1884 0000121C 3AFFFFFA bcc Rd_IO_portB_lp ; Carry set when counted out 1885 00001220 1886 00001220 E8BD0008 ldmfd sp!, {r3} ; 1887 00001224 E8BD8001 ldmfd sp!, {r0, pc} ; 1888 00001228 1889 00001228 E597E040 Rd_IO_RxD ldr r14, [r7, #Terminal_Rx_tail - shared_var iables] 1890 0000122C E597003C ldr r0, [r7, #Terminal_Rx_head - shared_var iables] 1891 00001230 E15E0000 cmp r14, r0 ; Buffer empty? 1892 00001234 05D71012 ldreqb r1, [r7, #Terminal_Rx_last - shared_vari ables] 1893 00001238 08BD8001 ldmeqfd sp!, {r0, pc} ; Duff read - get out 1894 0000123C 1895 0000123C E4DE1001 ldrb r1, [r14], #1 ; Else get from buffer 1896 00001240 E35E0094 cmp r14, #Terminal_Rx_buff_end - Mon_RAM_sta rt 1897 00001244 23A0E084 movhs r14, #Terminal_Rx_buff_start - Mon_RAM_s tart 1898 00001248 E587E040 str r14, [r7, #Terminal_Rx_tail - shared_var iables] 1899 0000124C E5C71012 strb r1, [r7, #Terminal_Rx_last - shared_var iables] 1900 00001250 1901 00001250 E15E0000 cmp r14, r0 ; Buffer now empty? 1902 00001254 05D7000E ldreqb r0, [r7, #interrupts_active - shared_var iables] 1903 00001258 03C00010 biceq r0, r0, #Int_Rx_ready ; Clear interrupt bit ARM Macro Assembler Page 66 1904 0000125C 05C7000E streqb r0, [r7, #interrupts_active - shared_var iables] 1905 00001260 1906 00001260 E8BD8001 ldmfd sp!, {r0, pc} ; 1907 00001264 1908 00001264 1909 00001264 Rd_IO_serial_status 1910 00001264 E597E040 ldr r14, [r7, #Terminal_Rx_tail - shared_var iables] 1911 00001268 E597003C ldr r0, [r7, #Terminal_Rx_head - shared_var iables] 1912 0000126C E15E0000 cmp r14, r0 ; Buffer empty? 1913 00001270 03A01000 moveq r1, #0 ; Set state of RxD 1914 00001274 13A01001 movne r1, #UART_RxRdy ; 1915 00001278 1916 00001278 E5970048 ldr r0, [r7, #Terminal_Tx_tail - shared_vari ables] 1917 0000127C E597E044 ldr r14, [r7, #Terminal_Tx_head - shared_var iables] 1918 00001280 E04E0000 sub r0, r14, r0 ; Head - Tail => occupancy(i sh) 1919 00001284 E350000F cmp r0, #Terminal_Tx_buff_end - Terminal_Tx_ buff_start - 1 1920 00001288 13700001 cmpne r0, #-1 ; All but caught up? 1921 0000128C ; Buffer full? 1922 0000128C 13811002 orrne r1, r1, #UART_TxRdy ; 1923 00001290 E8BD8001 ldmfd sp!, {r0, pc} ; 1924 00001294 1925 00001294 Rd_IO_Tube 1926 00001294 Rd_IO_none 1927 00001294 E3A0102A mov r1, #&2A ; "Abort", for now @@@ 1928 00001298 1929 00001298 E8BD8001 ldmfd sp!, {r0, pc} ; 1930 0000129C 1931 0000129C 1932 0000129C E3A00046 Rd_IO_irq mov r0, #interrupts_active - Mon_RAM_start 1933 000012A0 EAFFFFCC b Rd_IO_out ; Read byte and exit 1934 000012A4 1935 000012A4 E3A00047 Rd_IO_ien mov r0, #interrupts_enable - Mon_RAM_start 1936 000012A8 EAFFFFCA b Rd_IO_out ; Read byte and exit 1937 000012AC 1938 000012AC E3A00049 Rd_IO_timer_cmp mov r0, #timer_compare - Mon_RAM_start 1939 000012B0 EAFFFFC8 b Rd_IO_out ; Read byte and exit 1940 000012B4 1941 000012B4 E202000C Rd_serial_No and r0, r2, #&0C ; Get address bits in `word' 1942 000012B8 E1A00120 mov r0, r0, lsr #2 ; Address within word 1943 000012BC E2800038 add r0, r0, #Board_number - Mon_RAM_start 1944 000012C0 EAFFFFC4 b Rd_IO_out ; Read byte and exit 1945 000012C4 ARM Macro Assembler Page 67 1946 000012C4 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1947 000012C4 ; Address in R2, data in R1:R0 1948 000012C4 1949 000012C4 E52DE004 write_memory_d str lr, [sp, #-4]! ; May be faster than stm 1950 000012C8 1951 000012C8 E597E020 ldr r14, [r7, #mem_area_start - shared_varia bles] 1952 000012CC E152000E cmp r2, r14 ; 1953 000012D0 3A000033 blo write_memory_IO_D ; Address too low 1954 000012D4 E597E024 ldr r14, [r7, #mem_area_end - shared_variabl es] 1955 000012D8 E152000E cmp r2, r14 ; 1956 000012DC 2A000030 bhs write_memory_IO_D ; Address too high 1957 000012E0 1958 000012E0 E597E028 ldr r14, [r7, #mem_area_pos - shared_variabl es] 1959 000012E4 E782000E str r0, [r2, r14] ; Address in range 1960 000012E8 E28EE004 add r14, r14, #4 ; 1961 000012EC E782100E str r1, [r2, r14] ; High word 1962 000012F0 1963 000012F0 E49DF004 ldr pc, [sp], #4 ; May be faster than ldm 1964 000012F4 1965 000012F4 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1966 000012F4 ; Address in R2, data in R0 1967 000012F4 1968 000012F4 E52DE004 write_memory_w str lr, [sp, #-4]! ; May be faster than stm 1969 000012F8 1970 000012F8 E597E020 ldr r14, [r7, #mem_area_start - shared_varia bles] 1971 000012FC E152000E cmp r2, r14 ; 1972 00001300 3A000027 blo write_memory_IO_W ; Address too low 1973 00001304 E597E024 ldr r14, [r7, #mem_area_end - shared_variabl es] 1974 00001308 E152000E cmp r2, r14 ; 1975 0000130C 2A000024 bhs write_memory_IO_W ; Address too high 1976 00001310 1977 00001310 E597E028 ldr r14, [r7, #mem_area_pos - shared_variabl es] 1978 00001314 E782000E str r0, [r2, r14] ; Address in range 1979 00001318 1980 00001318 E49DF004 ldr pc, [sp], #4 ; May be faster than ldm 1981 0000131C 1982 0000131C ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1983 0000131C ; Address in R2, data in R0 1984 0000131C 1985 0000131C E52DE004 write_memory_h str lr, [sp, #-4]! ; May be faster than STM 1986 00001320 1987 00001320 E597E020 ldr r14, [r7, #mem_area_start - shared_varia bles] 1988 00001324 E152000E cmp r2, r14 ; ARM Macro Assembler Page 68 1989 00001328 3A000005 blo write_memory_h1 ; Address too low 1990 0000132C E597E024 ldr r14, [r7, #mem_area_end - shared_variabl es] 1991 00001330 E152000E cmp r2, r14 ; 1992 00001334 2A000002 bhs write_memory_h1 ; Address too high 1993 00001338 1994 00001338 E597E028 ldr r14, [r7, #mem_area_pos - shared_variabl es] 1995 0000133C E18200BE strh r0, [r2, r14] ; Address in range 1996 00001340 1997 00001340 E49DF004 ldr pc, [sp], #4 ; May be faster than LDM 1998 00001344 1999 00001344 write_memory_h1 2000 00001344 E202E20F and r14, r2, #&F0000000 ; Bodgery! @@ 2001 00001348 E35E0203 cmp r14, #Virtex_page ; Virtex? 2002 0000134C 1A000014 bne write_memory_IO_H ; Not Virtex 2003 00001350 2004 00001350 E3C2E20F bic r14, r2, #&F0000000 ; Find page offset 2005 00001354 E38EE202 orr r14, r14, #VIRTEX_base ; Find true address 2006 00001358 E5CE0000 strb r0, [r14] ; 2007 0000135C 2008 0000135C E49DF004 ldr pc, [sp], #4 ; May be faster than LDM 2009 00001360 2010 00001360 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2011 00001360 ; Address in R2, data in R0 2012 00001360 2013 00001360 E52DE004 write_memory_b str lr, [sp, #-4]! ; May be faster than STM 2014 00001364 2015 00001364 E597E020 ldr r14, [r7, #mem_area_start - shared_varia bles] 2016 00001368 E152000E cmp r2, r14 ; 2017 0000136C 3A000005 blo write_mem_b1 ; Address too low 2018 00001370 E597E024 ldr r14, [r7, #mem_area_end - shared_variabl es] 2019 00001374 E152000E cmp r2, r14 ; 2020 00001378 2A000002 bhs write_mem_b1 ; Address too high 2021 0000137C 2022 0000137C E597E028 ldr r14, [r7, #mem_area_pos - shared_variabl es] 2023 00001380 E7C2000E strb r0, [r2, r14] ; Address in range 2024 00001384 2025 00001384 E49DF004 ldr pc, [sp], #4 ; May be faster than LDM 2026 00001388 2027 00001388 write_mem_b1 2028 00001388 E202E20F and r14, r2, #&F0000000 ; Bodgery! @@ 2029 0000138C E35E0202 cmp r14, #Spartan_page ; Spartan? 2030 00001390 1A000003 bne write_memory_IO_B ; Not Spartan 2031 00001394 2032 00001394 E3C2E20F bic r14, r2, #&F0000000 ; Find page offset 2033 00001398 E38EE101 orr r14, r14, #SPARTAN_base ; Find true address 2034 0000139C E5CE0000 strb r0, [r14] ; 2035 000013A0 2036 000013A0 E49DF004 ldr pc, [sp], #4 ; May be faster than LDM 2037 000013A4 ARM Macro Assembler Page 69 2038 000013A4 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2039 000013A4 ; LR already stacked on entry 2040 000013A4 2041 000013A4 write_memory_IO_D ; Needs fixing @@@ 2042 000013A4 write_memory_IO_W 2043 000013A4 write_memory_IO_H 2044 000013A4 write_memory_IO_B 2045 000013A4 E3520403 cmp r2, #tube ; Test/verification port 2046 000013A8 0A000014 beq Wr_IO_Tube ; 2047 000013AC 2048 000013AC E3520201 cmp r2, #IO_area_start ; 2049 000013B0 3A00000A blo write_memory_abort ; Address too low 2050 000013B4 E3520202 cmp r2, #IO_area_end ; 2051 000013B8 2A000008 bhs write_memory_abort ; Address too high 2052 000013BC 2053 000013BC E3120003 tst r2, #3 ; 2054 000013C0 18BD8000 ldmnefd sp!, {pc} ; Return unless byte #0 2055 000013C4 2056 000013C4 E202E03C and r14, r2, #&3C ; Partial decode 2057 000013C8 2058 000013C8 E7DFE12E ldrb r14, [pc, r14, lsr #2] ; Get offset 2059 000013CC E08FF10E add pc, pc, r14, lsl #2 ; Multiply `offset' by 4 2060 000013D0 2061 000013D0 ; Relocatable jump table to different devices 2062 000013D0 1B DCB (Wr_IO_portA - %f1) / 4 ; 00 2063 000013D1 22 DCB (Wr_IO_portB - %f1) / 4 ; 04 2064 000013D2 07 DCB (Wr_IO_timer - %f1) / 4 ; 08 2065 000013D3 3C DCB (Wr_IO_timer_cmp-%f1)/4 ; 0C 2066 000013D4 1 ; One word into table 2067 000013D4 3E DCB (Wr_IO_TxD - %b1) / 4 ; 10 2068 000013D5 37 DCB (Wr_IO_none - %b1) / 4 ; 14 Reserved fo r serial control(?) 2069 000013D6 38 DCB (Wr_IO_irq - %b1) / 4 ; 18 2070 000013D7 3A DCB (Wr_IO_ien - %b1) / 4 ; 1C 2071 000013D8 16 DCB (Wr_IO_stop - %b1) / 4 ; 20 Next four a re serial number 2072 000013D9 37 DCB (Wr_IO_none - %b1) / 4 ; 24 2073 000013DA 37 DCB (Wr_IO_none - %b1) / 4 ; 28 2074 000013DB 37 DCB (Wr_IO_none - %b1) / 4 ; 2C 2075 000013DC 37 DCB (Wr_IO_none - %b1) / 4 ; 30 Reserved 2076 000013DD 37 DCB (Wr_IO_none - %b1) / 4 ; 34 2077 000013DE 37 DCB (Wr_IO_none - %b1) / 4 ; 38 2078 000013DF 37 DCB (Wr_IO_none - %b1) / 4 ; 3C 2079 000013E0 2080 000013E0 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2081 000013E0 2082 000013E0 write_memory_abort ; Not very finished! @@@ 2083 000013E0 2084 000013E0 E202E20F and r14, r2, #&F0000000 ; Hack to write Ethe rnet chip 2085 000013E4 E35E0203 cmp r14, #ETHERNET_base 2086 000013E8 01C200B0 streqh r0, [r2] ; 2087 000013EC 2088 000013EC 2089 000013EC E49DF004 ldr pc, [sp], #4 ; May be faster than ldm 2090 000013F0 ARM Macro Assembler Page 70 2091 000013F0 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2092 000013F0 2093 000013F0 E3A0E040 Wr_IO_timer mov r14, #Line_time_clk - Mon_RAM_start 2094 000013F4 E5CE0000 Wr_IO_R14 strb r0, [r14] ; 2095 000013F8 E8BD8000 ldmfd sp!, {pc} ; 2096 000013FC 2097 000013FC FFFCC000 Tube_line DCD US1_base ; Tube serial line definitio n 2098 00001400 2099 00001400 E3500004 Wr_IO_Tube cmp r0, #cEOT ; 2100 00001404 0A000008 beq Wr_IO_stop ; ^D stops execution 2101 00001408 2102 00001408 E51FE014 Wr_IO_Tube1 ldr r14, Tube_line ; Load rather than stack reg. 2103 0000140C E59EE014 ldr r14, [r14, #US_CSR] ; Pass byte to trans mit in R0 2104 00001410 E31E0002 tst r14, #TxRdy ; Test if ready to transmit 2105 00001414 1A000001 bne Wr_IO_Tube2 ; If set the output 2106 00001418 2107 00001418 E24FE018 adr lr, Wr_IO_Tube1 ; Set return address (loop) 2108 0000141C EAFFFCE0 b deschedule_ex ; Deschedule 2109 00001420 2110 00001420 E51FE02C Wr_IO_Tube2 ldr r14, Tube_line ; Reload rather than stac k ... 2111 00001424 E58E001C str r0, [r14, #US_THR] ; 2112 00001428 E8BD8000 ldmfd sp!, {pc} ; Return 2113 0000142C 2114 0000142C 2115 0000142C ; Special method of stopping emulator for verification p rog. 2116 0000142C E5D7E00C Wr_IO_stop ldrb r14, [r7, #arm_state - shared_variables] 2117 00001430 E5C7E00D strb r14, [r7, #arm_state_old - shared_variab les] 2118 00001434 E3A0E041 mov r14, #State_stop_req ; Set status to stop 2119 00001438 E5C7E00C strb r14, [r7, #arm_state - shared_variables] 2120 0000143C ; Signal to processor 2121 0000143C E8BD8000 ldmfd sp!, {pc} ; Return 2122 00001440 2123 00001440 2124 00001440 E92D0001 Wr_IO_portA stmfd sp!, {r0} ; Need another register ARM Macro Assembler Page 71 2125 00001444 E59FE0BC ldr r14, IO_PIO_base ; 2126 00001448 E20000FF and r0, r0, #&FF ; 2127 0000144C E58E0030 str r0, [r14, #PIO_SODR] ; Set selected outputs 2128 00001450 E22000FF eor r0, r0, #&FF ; 2129 00001454 E58E0034 str r0, [r14, #PIO_CODR] ; Clear other outputs 2130 00001458 E8BD8001 ldmfd sp!, {r0, pc} ; 2131 0000145C 2132 0000145C 2133 0000145C 2134 0000145C ; Write another selection of AT91 PIO lines 2135 0000145C E92D000F Wr_IO_portB stmfd sp!, {r0-r3} ; Need more space 2136 00001460 2137 00001460 E1A00C00 mov r0, r0, lsl #24 ; Left justify byte 2138 00001464 E3A01000 mov r1, #0 ; Accumulator 2139 00001468 E3A0E001 mov r14, #1 ; Bit mask 2140 0000146C E28F20A0 adr r2, IO_PIO_portB_tab ; Bit positions 2141 00001470 2142 00001470 E4D23001 Wr_IO_portB_lp ldrb r3, [r2], #1 ; Find next bit position 2143 00001474 E1B00080 movs r0, r0, lsl #1 ; Sets C and Z for below 2144 00001478 2181131E orrcs r1, r1, r14, lsl r3 ; Conditional bit set 2145 0000147C 1AFFFFFB bne Wr_IO_portB_lp ; Continue for all set bits 2146 00001480 2147 00001480 E59F0088 ldr r0, IO_PIO_portB_inv ; 2148 00001484 E0211000 eor r1, r1, r0 ; Invert some bits 2149 00001488 2150 00001488 E59FE078 ldr r14, IO_PIO_base ; 2151 0000148C 2152 0000148C E3A030FF mov r3, #&FF ; Port A bit mask 2153 00001490 E3110402 tst r1, #AT91_LCD_RW ; Check if R/~W going high 2154 00001494 158E3014 strne r3, [r14, #PIO_ODR] ; If so, disable portA o/p 2155 00001498 2156 00001498 E59F006C ldr r0, IO_PIO_portB ; 2157 0000149C ; and r1, r1, r0 ; Should be superfluous @@@ 2158 0000149C E58E1030 str r1, [r14, #PIO_SODR] ; Set selected outputs 2159 000014A0 E0211000 eor r1, r1, r0 ; Flip relevant bits 2160 000014A4 E58E1034 str r1, [r14, #PIO_CODR] ; Clear other outputs 2161 000014A8 2162 000014A8 058E3010 streq r3, [r14, #PIO_OER] ; If safe, enable portA o/p 2163 000014AC 2164 000014AC E8BD800F ldmfd sp!, {r0-r3, pc} ; 2165 000014B0 2166 000014B0 2167 000014B0 Wr_IO_none ; @@@ 2168 000014B0 E8BD8000 ldmfd sp!, {pc} ; 2169 000014B4 ARM Macro Assembler Page 72 2170 000014B4 2171 000014B4 E3A0E046 Wr_IO_irq mov r14, #interrupts_active - Mon_RAM_start 2172 000014B8 EAFFFFCD b Wr_IO_R14 ; strb r0, [r14] & return 2173 000014BC 2174 000014BC E3A0E047 Wr_IO_ien mov r14, #interrupts_enable - Mon_RAM_start 2175 000014C0 EAFFFFCB b Wr_IO_R14 ; strb r0, [r14] & return 2176 000014C4 2177 000014C4 E3A0E049 Wr_IO_timer_cmp mov r14, #timer_compare - Mon_RAM_start 2178 000014C8 EAFFFFC9 b Wr_IO_R14 ; strb r0, [r14] & return 2179 000014CC 2180 000014CC E5971048 Wr_IO_TxD ldr r1, [r7, #Terminal_Tx_tail - shared_vari ables] 2181 000014D0 E5972044 ldr r2, [r7, #Terminal_Tx_head - shared_vari ables] 2182 000014D4 ; sub r1, r2, r1 ; Head - Tail => occupancy(ish) 2183 000014D4 ; cmp r1, #Terminal_Tx_buff_end - Terminal_Tx_buff_star t - 1 2184 000014D4 ; cmpne r1, #-1 ; All but caught up? 2185 000014D4 2186 000014D4 E0411002 sub r1, r1, r2 ; Tail - Head => free space( ish) 2187 000014D8 E2511001 subs r1, r1, #1 ; (At least) one space alway s free 2188 000014DC 42911010 addmis r1, r1, #Terminal_Tx_buff_end - Terminal _Tx_buff_start 2189 000014E0 2190 000014E0 08BD8000 ldmeqfd sp!, {pc} ; Buffer already full - reje ct 2191 000014E4 2192 000014E4 E4C20001 strb r0, [r2], #1 ; Buffer byte, post increme nt 2193 000014E8 E35200A4 cmp r2, #Terminal_Tx_buff_end - Mon_RAM_star t 2194 000014EC 23A02094 movhs r2, #Terminal_Tx_buff_start - Mon_RAM_st art 2195 000014F0 E5872044 str r2, [r7, #Terminal_Tx_head - shared_vari ables] 2196 000014F4 2197 000014F4 E3510001 cmp r1, #1 ; Buffer now full? 2198 000014F8 05D7000E ldreqb r0, [r7, #interrupts_active - shared_var iables] 2199 000014FC 03C00020 biceq r0, r0, #Int_Tx_ready ; Clear interrupt bit 2200 00001500 05C7000E streqb r0, [r7, #interrupts_active - shared_var iables] 2201 00001504 2202 00001504 E8BD8000 ldmfd sp!, {pc} ; 2203 00001508 2204 00001508 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2205 00001508 ; Literal pool ARM Macro Assembler Page 73 2206 00001508 2207 00001508 FFFF0000 IO_PIO_base DCD PIO_base ; 2208 0000150C 2209 0000150C 439C0000 IO_PIO_portB DCD &439C0000 ; Port B allowed bits 2210 00001510 401C0000 IO_PIO_portB_inv DCD &401C0000 ; Port B inverted bits 2211 00001514 2212 00001514 13 IO_PIO_portB_tab DCB 19 ; Bit #7 LHS button 2213 00001515 12 DCB 18 ; Bit #6 RHS button 2214 00001516 14 DCB 20 ; Bit #5 LCD backlight 2215 00001517 1E DCB 30 ; Bit #4 LED enable 2216 00001518 20 DCB 32 ; Bit #3 (always zero) 2217 00001519 19 DCB 25 ; Bit #2 LCD R/~W 2218 0000151A 17 DCB 23 ; Bit #1 LCD RS 2219 0000151B 18 DCB 24 ; Bit #0 LCD En 2220 0000151C 2221 0000151C ALIGN 2222 0000151C 2223 0000151C ;------------------------------------------------------- ----------------------- 2224 0000151C 2225 0000151C E92D4000 reverse_byte stmfd sp!, {lr} ; Bit reverse byte in R0 2226 00001520 E3A0E401 mov r14, #&01000000 ; Accumulator & bit counter 2227 00001524 2228 00001524 E1B000A0 reverse_byte1 movs r0, r0, lsr #1 ; LSB into carry 2229 00001528 E0BEE00E adcs r14, r14, r14 ; Shift left from carry 2230 0000152C 3AFFFFFC bcc reverse_byte1 ; Carry set to terminate 2231 00001530 2232 00001530 E1A0000E mov r0, r14 ; 2233 00001534 E8BD8000 ldmfd sp!, {pc} ; 2234 00001538 2235 00001538 ;------------------------------------------------------- ----------------------- 2236 00001538 2237 00001538 E92D4004 Host_get_double stmfd sp!, {r2, lr} ; Returns R1:R0 2238 0000153C EB000009 bl Host_get_word ; 2239 00001540 E1A02000 mov r2, r0 ; Low word 2240 00001544 EB000007 bl Host_get_word ; 2241 00001548 E1A01000 mov r1, r0 ; High word 2242 0000154C E1A00002 mov r0, r2 ; 2243 00001550 E8BD8004 ldmfd sp!, {r2, pc} ; 2244 00001554 2245 00001554 E92D4001 Host_put_double stmfd sp!, {r0, lr} ; 2246 00001558 EB00000F bl Host_put_word ; ARM Macro Assembler Page 74 2247 0000155C E1A00001 mov r0, r1 ; High word 2248 00001560 EB00000D bl Host_put_word ; 2249 00001564 E8BD8001 ldmfd sp!, {r0, pc} ; 2250 00001568 2251 00001568 E92D4002 Host_get_word stmfd sp!, {r1, lr} ; 2252 0000156C EB000027 bl Host_in ; 2253 00001570 E1A01000 mov r1, r0 ; 2254 00001574 EB000025 bl Host_in ; 2255 00001578 E1811400 orr r1, r1, r0, lsl #8 ; 2256 0000157C EB000023 bl Host_in ; 2257 00001580 E1811800 orr r1, r1, r0, lsl #16 ; 2258 00001584 EB000021 bl Host_in ; 2259 00001588 E1810C00 orr r0, r1, r0, lsl #24 ; 2260 0000158C E8BD8002 ldmfd sp!, {r1, pc} ; 2261 00001590 2262 00001590 Host_put_halfword 2263 00001590 E92D4005 stmfd sp!, {r0, r2, lr} ; 2264 00001594 E3A02002 mov r2, #2 ; Byte count 2265 00001598 EA000001 b Host_put_N ; 2266 0000159C 2267 0000159C E92D4005 Host_put_word stmfd sp!, {r0, r2, lr} ; 2268 000015A0 E3A02004 mov r2, #4 ; Byte count 2269 000015A4 EB000010 Host_put_N bl Host_out ; Also an entry point 2270 000015A8 E1A00420 mov r0, r0, lsr #8 ; Next byte 2271 000015AC E2522001 subs r2, r2, #1 ; 2272 000015B0 8AFFFFFB bhi Host_put_N ; 2273 000015B4 E8BD8005 ldmfd sp!, {r0, r2, pc} ; 2274 000015B8 2275 000015B8 Host_get_halfword 2276 000015B8 E92D4002 stmfd sp!, {r1, lr} ; 2277 000015BC EB000013 bl Host_in ; 2278 000015C0 E1A01000 mov r1, r0 ; 2279 000015C4 EB000011 bl Host_in ; 2280 000015C8 E1810400 orr r0, r1, r0, lsl #8 ; 2281 000015CC E8BD8002 ldmfd sp!, {r1, pc} ; 2282 000015D0 2283 000015D0 ;------------------------------------------------------- ----------------------- 2284 000015D0 ; This serial code relies on the head and tail pointers being `close' in memory 2285 000015D0 ; and various other values being representable as single immediates. 2286 000015D0 2287 000015D0 Host_buffer_init 2288 000015D0 E92D4001 stmfd sp!, {r0, lr} ; 2289 000015D4 E3A0E020 mov r14, #Host_buffer_head - Mon_RAM_start 2290 000015D8 ; Crude hack method for now @@@ 2291 000015D8 E3A00028 mov r0, #Host_buffer_start - Mon_RAM_start 2292 000015DC E58E0000 str r0, [r14] ; Initialise head 2293 000015E0 E58E0004 str r0, [r14, #Host_buffer_tail - Host_buffe r_head] 2294 000015E4 ; Initialise tail 2295 000015E4 E8BD8001 ldmfd sp!, {r0, pc} ; ARM Macro Assembler Page 75 2296 000015E8 2297 000015E8 FFFD0000 Host_line DCD US0_base ; Host serial line definitio n 2298 000015EC ; Also needs changes in Mon_init_table! 2299 000015EC ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2300 000015EC ; Send character in R0 to host serial line 2301 000015EC ; Offer descheduling point if transmitter busy 2302 000015EC 2303 000015EC E92D4002 Host_out stmfd sp!, {r1, lr} ; 2304 000015F0 E51F1010 ldr r1, Host_line ; Pointer to UART 2305 000015F4 2306 000015F4 E591E014 Host_out1 ldr r14, [r1, #US_CSR] ; R14 is a scratch re gister here 2307 000015F8 E31E0002 tst r14, #TxRdy ; Test if ready to transmit 2308 000015FC 1A000001 bne Host_out2 ; 2309 00001600 2310 00001600 E24FE014 adr lr, Host_out1 ; Set return address 2311 00001604 EAFFFC6B b deschedule_com ; 2312 00001608 2313 00001608 E581001C Host_out2 str r0, [r1, #US_THR] ; Send character 2314 0000160C E8BD8002 ldmfd sp!, {r1, pc} ; 2315 00001610 2316 00001610 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2317 00001610 ; Get character from host serial line buffer into R0 2318 00001610 ; Offer descheduling point if nothing pending 2319 00001610 2320 00001610 E92D4006 Host_in stmfd sp!, {r1-r2, lr} ; 2321 00001614 E3A02020 mov r2, #Host_buffer_head - Mon_RAM_start 2322 00001618 ; Crude hack method for now @@@ 2323 00001618 E5921004 ldr r1, [r2, #Host_buffer_tail - Host_buffer _head] 2324 0000161C ; Get tail 2325 0000161C E5920000 Host_in1 ldr r0, [r2] ; Get head 2326 00001620 E1500001 cmp r0, r1 ; Pointers equal for empty 2327 00001624 1A000001 bne Host_in_rdy ; 2328 00001628 2329 00001628 E24FE014 adr lr, Host_in1 ; Return address 2330 0000162C EAFFFC61 b deschedule_com ; 2331 00001630 2332 00001630 E4D10001 Host_in_rdy ldrb r0, [r1], #1 ; Read character, move poin ter 2333 00001634 E3510038 cmp r1, #Host_buffer_end - Mon_RAM_start ; but still wrap 2334 00001638 23A01028 movhs r1, #Host_buffer_start - Mon_RAM_start ARM Macro Assembler Page 76 2335 0000163C E5821004 str r1, [r2, #Host_buffer_tail - Host_buffer _head] 2336 00001640 ; Save new tail 2337 00001640 2338 00001640 E8BD8006 ldmfd sp!, {r1-r2, pc} ; 2339 00001644 2340 00001644 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2341 00001644 ; Timer 0 interrupt service routine 2342 00001644 2343 00001644 E24EE004 Timer0_isr sub lr, lr, #4 ; Correct return address 2344 00001648 E92D4003 stmfd sp!, {r0-r1, lr} ; 2345 0000164C 2346 0000164C E59F110C ldr r1, Lit_TC0_base ; 2347 00001650 E5911020 ldr r1, [r1, #TC_SR] ; Read status to clear interrupt 2348 00001654 2349 00001654 E3A01000 mov r1, #FASTRAM_base ; (a.k.a. 00000000) 2350 00001658 E591E040 ldr r14, [r1, #Line_time_clk - Mon_RAM_start ] 2351 0000165C E28EE001 add r14, r14, #1 ; Increment clock 2352 00001660 E581E040 str r14, [r1, #Line_time_clk - Mon_RAM_start ] 2353 00001664 2354 00001664 E5D10049 ldrb r0, [r1, #timer_compare - Mon_RAM_start] 2355 00001668 E20EE0FF and r14, r14, #&FF ; Use only one byte 2356 0000166C E130000E teq r0, r14 ; Timer at target value? 2357 00001670 2358 00001670 E5D10046 ldrb r0, [r1, #interrupts_active - Mon_RAM_st art] 2359 00001674 03800001 orreq r0, r0, #Int_timer_compare ; Set ... 2360 00001678 13C00001 bicne r0, r0, #Int_timer_compare ; ... or clear bit 2361 0000167C E5C10046 strb r0, [r1, #interrupts_active - Mon_RAM_st art] 2362 00001680 2363 00001680 E59F10D4 ldr r1, Lit_AIC_base ; 2364 00001684 E581E130 str r14, [r1, #AIC_EOICR] ; Signal end of interrupt 2365 00001688 2366 00001688 E8FD8003 ldmfd sp!, {r0-r1, pc}^ ; Return from interrupt 2367 0000168C 2368 0000168C ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2369 0000168C 2370 0000168C E24EE004 PIO_isr sub lr, lr, #4 ; Correct return address 2371 00001690 E92D4007 stmfd sp!, {r0-r2, lr} ; 2372 00001694 2373 00001694 ; mov r14, #RAM_base ; Indicates ISR called once on sta rtup 2374 00001694 ; ldr r1, [r14] ; Is the initialisation incomplete? @@@ 2375 00001694 ; add r1, r1, #1 2376 00001694 ; str r1, [r14] 2377 00001694 ARM Macro Assembler Page 77 2378 00001694 E51FE194 ldr r14, IO_PIO_base ; 2379 00001698 E3A01000 mov r1, #0 ; 2380 0000169C E59E004C ldr r0, [r14, #PIO_ISR] ; Clear interrupt 2381 000016A0 E59E003C ldr r0, [r14, #PIO_PDSR] ; Read pin status 2382 000016A4 2383 000016A4 E3A0E000 mov r14, #FASTRAM_base ; (a.k.a. 00000000) 2384 000016A8 2385 000016A8 E3100702 tst r0, #AT91_Virtex_init ; Test ports & translate 2386 000016AC 03811080 orreq r1, r1, #Int_L_button ; Active low 2387 000016B0 E3100701 tst r0, #AT91_Spartan_init ; 2388 000016B4 03811040 orreq r1, r1, #Int_R_button ; Active low 2389 000016B8 E3100B02 tst r0, #AT91_Ether_IRQ ; 2390 000016BC 13811008 orrne r1, r1, #Int_Ethernet ; Active high 2391 000016C0 E3100B01 tst r0, #AT91_Virtex_IRQ ; 2392 000016C4 03811004 orreq r1, r1, #Int_Virtex ; Active low (?) 2393 000016C8 E3100C02 tst r0, #AT91_Spartan_IRQ ; 2394 000016CC 03811002 orreq r1, r1, #Int_Spartan ; Active low (?) 2395 000016D0 2396 000016D0 E5DE2048 ldrb r2, [r14, #Last_PIO_IRQ_state - Mon_RAM_ start] 2397 000016D4 E5CE1048 strb r1, [r14, #Last_PIO_IRQ_state - Mon_RAM_ start] 2398 000016D8 2399 000016D8 E1C20001 bic r0, r2, r1 ; Bit mask to clear 2400 000016DC E1C11002 bic r1, r1, r2 ; Bit mask to set 2401 000016E0 2402 000016E0 E5DE2046 ldrb r2, [r14, #interrupts_active - Mon_RAM_s tart] 2403 000016E4 E1C22000 bic r2, r2, r0 ; Clear some bits 2404 000016E8 E1822001 orr r2, r2, r1 ; Set some bits 2405 000016EC E5CE2046 strb r2, [r14, #interrupts_active - Mon_RAM_s tart] 2406 000016F0 2407 000016F0 E59FE064 ldr r14, Lit_AIC_base ; 2408 000016F4 E58EE130 str r14, [r14, #AIC_EOICR] ; Signal end of interrupt 2409 000016F8 2410 000016F8 E8FD8007 ldmfd sp!, {r0-r2, pc}^ ; Return from interrupt 2411 000016FC 2412 000016FC ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2413 000016FC 2414 000016FC E24EE004 Host_isr sub lr, lr, #4 ; Correct return address 2415 00001700 E92D400D stmfd sp!, {r0, r2-r3, lr} ; 2416 00001704 2417 00001704 E51FE124 ldr r14, Host_line ; Stacked; now use as scr atch 2418 00001708 2419 00001708 E59E0014 ldr r0, [r14, #US_CSR] ; Read status register 2420 0000170C E3100001 tst r0, #RxRdy ; Only source so far 2421 00001710 0A000009 beq Host_isr_out ; Just in case 2422 00001714 2423 00001714 E3A02020 mov r2, #Host_buffer_head - Mon_RAM_start 2424 00001718 ; Crude hack method for now @@@ ARM Macro Assembler Page 78 2425 00001718 E5923000 ldr r3, [r2] ; Head of buffer 2426 0000171C 2427 0000171C E59E0018 Host_isr_1 ldr r0, [r14, #US_RHR] ; Get character 2428 00001720 2429 00001720 ; The following cares nothing for overruns! 2430 00001720 E4C30001 strb r0, [r3], #1 ; Store character, inc. poi nter 2431 00001724 E3530038 cmp r3, #Host_buffer_end - Mon_RAM_start 2432 00001728 23A03028 movhs r3, #Host_buffer_start - Mon_RAM_start 2433 0000172C 2434 0000172C E59E0014 ldr r0, [r14, #US_CSR] ; Check that no more characters 2435 00001730 E3100001 tst r0, #RxRdy ; are pending 2436 00001734 1AFFFFF8 bne Host_isr_1 ; Oops - repeat! 2437 00001738 2438 00001738 E5823000 str r3, [r2] ; Save new head 2439 0000173C 2440 0000173C E59FE018 Host_isr_out ldr r14, Lit_AIC_base ; 2441 00001740 E58E0130 str r0, [r14, #AIC_EOICR] ; Signal end of interrupt 2442 00001744 2443 00001744 E8FD800D ldmfd sp!, {r0, r2-r3, pc}^ ; Return from interrupt 2444 00001748 2445 00001748 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2446 00001748 ; Spurious interrupt trap code @@@ revise? @@@ 2447 00001748 2448 00001748 E24EE004 spurious_isr sub lr, lr, #4 ; Correct return address 2449 0000174C E52DE004 str lr, [sp, #-4]! ; May be faster than STM 2450 00001750 ; stmfd sp!, {lr} ; 2451 00001750 2452 00001750 E59FE004 ldr r14, Lit_AIC_base ; 2453 00001754 E581E130 str r14, [r1, #AIC_EOICR] ; Signal end of interrupt 2454 00001758 2455 00001758 E8FD8000 ldmfd sp!, {pc}^ ; Return from interrupt 2456 0000175C 2457 0000175C ;------------------------------------------------------- ----------------------- 2458 0000175C 2459 0000175C FFFFF000 Lit_AIC_base DCD AIC_base ; 2460 00001760 FFFE0000 Lit_TC0_base DCD TC_base + TC_CHL0 ; 2461 00001764 2462 00001764 ;------------------------------------------------------- ----------------------- 2463 00001764 2464 00001764 E3A07038 execute_start ARM Macro Assembler Page 79 mov r7, #shared_variables - Mon_RAM_start 2465 00001768 2466 00001768 ; Init. breakpoints here? @@@ 2467 00001768 2468 00001768 E3A00000 mov r0, #State_hard_reset ; Hardware reset state 2469 0000176C EA000001 b Reset_common ; 2470 00001770 2471 00001770 E3A07038 Reset mov r7, #shared_variables - Mon_RAM_start ; Superfluous?? 2472 00001774 E3A00001 mov r0, #State_reset ; Soft reset state 2473 00001778 E5C7000C Reset_common strb r0, [r7, #arm_state - shared_variables] 2474 0000177C E3A00000 mov r0, #0 ; No of steps pending 2475 00001780 E5870014 str r0, [r7, #arm_step_count - shared_variab les] 2476 00001784 E5870018 str r0, [r7, #arm_instr_count - shared_varia bles] 2477 00001788 2478 00001788 E3A0B000 mov r11, #Reset_PC ; PC 2479 0000178C E3A0C0D3 mov r12, #Reset_CPSR ; flags 2480 00001790 2481 00001790 E589C0A8 str r12, [r9, #sim_CPSR - reg_block] ; CPSR into dustbin 2482 00001794 E589B0AC str r11, [r9, #sim_PC - reg_block] ; Make PC visible 2483 00001798 2484 00001798 ; Point R7 at shared variables 2485 00001798 ; 00-3F = Reset 2486 00001798 ; 40-7F = Stopped 2487 00001798 ; 80-BF = Running 2488 00001798 ; C0-FF = Stepping 2489 00001798 ; Add breakpoint stuff later .. :-( 2490 00001798 ; Add temporary breakpoint (step until ...) 2491 00001798 2492 00001798 E3A00000 mov r0, #FALSE ; Disable breakpoints for fu ture 2493 0000179C E5C70030 strb r0, [r7, #break_enable - shared_variabl es] 2494 000017A0 2495 000017A0 2496 000017A0 E3A00000 Go_idle mov r0, #FALSE ; Disable breakpoints for mo ment 2497 000017A4 E5C70031 strb r0, [r7, #break_enabled - shared_variabl es] 2498 000017A8 2499 000017A8 ; Use "run with breakpoints" to allow "run until" - esp. for running procedure calls 2500 000017A8 ; @@@ ?? 2501 000017A8 2502 000017A8 E599C0A8 Idle_loop ldr r12, [r9, #sim_CPSR - reg_block] ; CPSR reload 2503 000017AC E599B0AC ldr r11, [r9, #sim_PC - reg_block] ; PC reload ARM Macro Assembler Page 80 2504 000017B0 E597802C ldr r8, [r7, #Running_flags - shared_variabl es] 2505 000017B4 ; This is in case these values have been modified remote ly 2506 000017B4 2507 000017B4 E28F3000 adr r3, Idle_loop1 ; (Really superfluous) 2508 000017B8 EB000062 bl Interrupt_check ; 2509 000017BC 2510 000017BC EBFFFBF8 Idle_loop1 bl deschedule_ex ; 2511 000017C0 E5D7000C ldrb r0, [r7, #arm_state - shared_variables] 2512 000017C4 ; Load command 2513 000017C4 E3500002 cmp r0, #State_to_reset ; Reset commanded? 2514 000017C8 0AFFFFE8 beq Reset ; Reboot 2515 000017CC 2516 000017CC E3100080 tst r0, #&80 ; Bit clear if stopped 2517 000017D0 0AFFFFF4 beq Idle_loop ; Remain stopped 2518 000017D4 2519 000017D4 E3100040 tst r0, #&40 ; Run or step? 2520 000017D8 1A00000E bne Step_loop ; Step commanded 2521 000017DC ; or fall into ... 2522 000017DC 2523 000017DC ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2524 000017DC 2525 000017DC E599C0A8 Run_loop ldr r12, [r9, #sim_CPSR - reg_block] ; CPSR reload 2526 000017E0 E599B0AC ldr r11, [r9, #sim_PC - reg_block] ; PC reload 2527 000017E4 2528 000017E4 E597802C ldr r8, [r7, #Running_flags - shared_variabl es] 2529 000017E8 2530 000017E8 E28F3008 adr r3, Run_loop1 ; Alternate `return' address 2531 000017EC EB000055 bl Interrupt_check ; 2532 000017F0 EB00007D bl fetch ; 2533 000017F4 ; Trap BL, SWI as in step routine ?? @@@ 2534 000017F4 2B00008C blcs step ; If no breakpoint 2535 000017F8 2536 000017F8 E589C0A8 Run_loop1 str r12, [r9, #sim_CPSR - reg_block] ; CPSR into dustbin 2537 000017FC E589B0AC str r11, [r9, #sim_PC - reg_block] ; Make PC visible 2538 00001800 2539 00001800 EBFFFBE7 bl deschedule_ex ; Deschedule 2540 00001804 2541 00001804 E5D7000C ldrb r0, [r7, #arm_state - shared_variables] 2542 00001808 E3100080 tst r0, #&80 ; Stopped? 2543 0000180C 0AFFFFE3 beq Go_idle ; Yes, stop 2544 00001810 2545 00001810 E3100040 tst r0, #&40 ; Run or step? 2546 00001814 0AFFFFF0 beq Run_loop ; Continue running ARM Macro Assembler Page 81 2547 00001818 ; or fall into ... 2548 00001818 2549 00001818 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2550 00001818 2551 00001818 E599C0A8 Step_loop ldr r12, [r9, #sim_CPSR - reg_block] ; CPSR reload 2552 0000181C E599B0AC ldr r11, [r9, #sim_PC - reg_block] ; PC reload 2553 00001820 2554 00001820 E597802C ldr r8, [r7, #Running_flags - shared_variabl es] 2555 00001824 2556 00001824 E28F3018 adr r3, Step_loop2 ; Alternate `return' address 2557 00001828 EB000046 bl Interrupt_check ; 2558 0000182C EB00006E bl fetch ; 2559 00001830 3A000003 bcc Step_loop2 ; Breakpoint found 2560 00001834 2561 00001834 E20A040B and r0, r10, #&0B000000 ; 2562 00001838 E350040B cmp r0, #&0B000000 ; BL or SWI instruction? 2563 0000183C 0A000011 beq step_call ; Yes - what now? 2564 00001840 2565 00001840 EB000079 Step_loop1 bl step ; If no breakpoint 2566 00001844 2567 00001844 E589C0A8 Step_loop2 str r12, [r9, #sim_CPSR - reg_block] ; CPSR into dustbin 2568 00001848 E589B0AC str r11, [r9, #sim_PC - reg_block] ; Make PC visible 2569 0000184C 2570 0000184C EBFFFBD4 bl deschedule_ex ; Deschedule 2571 00001850 2572 00001850 E5D7000C ldrb r0, [r7, #arm_state - shared_variables] 2573 00001854 2574 00001854 E3100080 tst r0, #&80 ; Stopped? 2575 00001858 0AFFFFD0 beq Go_idle ; So stop! 2576 0000185C 2577 0000185C E3100040 tst r0, #&40 ; Run or step? 2578 00001860 0AFFFFDD beq Run_loop ; Stop counting 2579 00001864 2580 00001864 E5970014 ldr r0, [r7, #arm_step_count - shared_variab les] 2581 00001868 E2500001 subs r0, r0, #1 ; Decrement count (& set fla gs) 2582 0000186C E5870014 str r0, [r7, #arm_step_count - shared_variab les] 2583 00001870 1AFFFFE8 bne Step_loop ; 2584 00001874 2585 00001874 E5D7000C ldrb r0, [r7, #arm_state - shared_variables] 2586 00001878 E5C7000D strb r0, [r7, #arm_state_old - shared_variabl es] 2587 0000187C E3A00043 mov r0, #State_count_out ; Stopped `command' ARM Macro Assembler Page 82 2588 00001880 E5C7000C strb r0, [r7, #arm_state - shared_variables] 2589 00001884 ; into command word 2590 00001884 2591 00001884 EAFFFFC5 b Go_idle ; If complete, stop 2592 00001888 2593 00001888 2594 00001888 ; Deal with potential running state change out of main e xecution path 2595 00001888 E31A0301 step_call tst r10, #&04000000 ; BL or SWI? 2596 0000188C 1A000003 bne step_call1 ; 2597 00001890 E3180002 tst r8, #Run_P_bit ; BL instruction detected 2598 00001894 0AFFFFE9 beq Step_loop1 ; 2599 00001898 E3A04081 mov r4, #State_running_BL ; 2600 0000189C 1A000002 bne step_call2 ; 2601 000018A0 2602 000018A0 E3180004 step_call1 tst r8, #Run_S_bit ; SWI instruction detected 2603 000018A4 0AFFFFE5 beq Step_loop1 ; 2604 000018A8 E3A04082 mov r4, #State_running_SWI ; 2605 000018AC 2606 000018AC E28FE01C step_call2 adr lr, Proc_loop1 ; `Return' address 2607 000018B0 EA000043 b Save_state ; Save PC++ & change to stat e R4 2608 000018B4 2609 000018B4 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2610 000018B4 2611 000018B4 E599C0A8 Procedure_loop ldr r12, [r9, #sim_CPSR - reg_block] ; CPSR reload 2612 000018B8 E599B0AC ldr r11, [r9, #sim_PC - reg_block] ; PC reload 2613 000018BC 2614 000018BC E3CBB003 bic r11, r11, #3 ; Align PC 2615 000018C0 E1A0200B mov r2, r11 ; PC 2616 000018C4 EBFFFDF3 bl read_memory_w ; Instruction fetch 2617 000018C8 E1A0A001 mov r10, r1 ; Instruction register 2618 000018CC E28BB004 add r11, r11, #4 ; and increment 2619 000018D0 2620 000018D0 EB000055 Proc_loop1 bl step ; Regardless of breakpoints! 2621 000018D4 2622 000018D4 E589C0A8 Proc_loop2 str r12, [r9, #sim_CPSR - reg_block] ; CPSR into dustbin 2623 000018D8 E589B0AC str r11, [r9, #sim_PC - reg_block] ; Make PC visible ARM Macro Assembler Page 83 2624 000018DC 2625 000018DC EBFFFBB0 bl deschedule_ex ; Deschedule 2626 000018E0 2627 000018E0 E5D7000C ldrb r0, [r7, #arm_state - shared_variables] 2628 000018E4 E3100080 tst r0, #&80 ; Stopped? 2629 000018E8 0AFFFFAC beq Go_idle ; Yes, stop 2630 000018EC 2631 000018EC E3100040 tst r0, #&40 ; Run or step? 2632 000018F0 1AFFFFC8 bne Step_loop ; Step commanded 2633 000018F4 2634 000018F4 E3500080 cmp r0, #State_running ; 2635 000018F8 0AFFFFB7 beq Run_loop ; Run commanded 2636 000018FC 2637 000018FC E3A06F55 mov r6, #exec_variables - Mon_RAM_start 2638 00001900 E5960008 ldr r0, [r6, #run_until_PC - exec_variables] 2639 00001904 E15B0000 cmp r11, r0 ; PC = return address? 2640 00001908 1AFFFFE9 bne Procedure_loop ; No 2641 0000190C 2642 0000190C E5D60010 ldrb r0, [r6, #run_until_mode - exec_variable s] 2643 00001910 E20C103F and r1, r12, #&3F ; Mode is same? 2644 00001914 E1510000 cmp r1, r0 ; 2645 00001918 1AFFFFE5 bne Procedure_loop ; No 2646 0000191C 2647 0000191C E596000C ldr r0, [r6, #run_until_SP - exec_variables] 2648 00001920 E5991034 ldr r1, [r9, #sim_R13 - reg_block] 2649 00001924 E1510000 cmp r1, r0 ; SP = as called 2650 00001928 1AFFFFE1 bne Procedure_loop ; No 2651 0000192C 2652 0000192C ; @@@ Is this right ??? Here?? 2653 0000192C ; Copy breakpoints -should be enabled- flag to enabled p osition 2654 0000192C E5D70030 ldrb r0, [r7, #break_enable - shared_variabl es] 2655 00001930 E5C70031 strb r0, [r7, #break_enabled - shared_variabl es] 2656 00001934 ; Always allows stepping of first instruction. 2657 00001934 2658 00001934 ; Pick up old state, restore and return as appropriate 2659 00001934 E5D60011 ldrb r0, [r6, #run_until_mode + 1 - exec_vari ables] 2660 00001938 E5C7000C strb r0, [r7, #arm_state - shared_variables] 2661 0000193C 2662 0000193C E7DF0320 ldrb r0, [pc, r0, lsr #6] 2663 00001940 E04FF100 sub pc, pc, r0, lsl #2 2664 00001944 2665 00001944 63 DCB (%f1 - Idle_loop1) / 4 ; All short backw ards offsets 2666 00001945 63 DCB (%f1 - Idle_loop1) / 4 ; 2667 00001946 54 DCB (%f1 - Run_loop1 ) / 4 ; 2668 00001947 41 DCB (%f1 - Step_loop2) / 4 ; 2669 00001948 1 2670 00001948 2671 00001948 2672 00001948 ; mov r0, r0, lsr #6 ; Get top 2 bits of old mode 2673 00001948 ; 2674 00001948 ; ldr r0, [pc, r0, lsl #2] ; N.B. no table offset 2675 00001948 ; add pc, pc, r0 ; Despatch as appropriate to mode 2676 00001948 ; ARM Macro Assembler Page 84 2677 00001948 ; DCD Idle_loop1 - %f1 ; 2678 00001948 ;1 2679 00001948 ; DCD Idle_loop1 - %b1 ; 2680 00001948 ; DCD Run_loop1 - %b1 ; 2681 00001948 ; DCD Step_loop2 - %b1 ; 2682 00001948 2683 00001948 ;------------------------------------------------------- ----------------------- 2684 00001948 ; R8 holds running flags 2685 00001948 ; Returns to LR if no enabled interrupts active 2686 00001948 ; Returns to R3 if enabled interrupts active while runni ng/stepping 2687 00001948 ; unless ISR `called', when it jumps to the procedure h andler 2688 00001948 2689 00001948 E51F0448 Interrupt_check ldr r0, IO_PIO_base ; 2690 0000194C E590003C ldr r0, [r0, #PIO_PDSR] ; Get pin state 2691 00001950 2692 00001950 E3100A01 tst r0, #nFIQ_wire ; 2693 00001954 1A000001 bne Int_chk1 ; FIQ inactive 2694 00001958 E31C0040 tst r12, #F_bit ; Interrupt disable flag 2695 0000195C 0A000010 beq enabled_FIQ ; 2696 00001960 2697 00001960 E31C0080 Int_chk1 tst r12, #I_bit ; Interrupts enabled? 2698 00001964 11A0F00E movne pc, lr ; No 2699 00001968 2700 00001968 E3A01000 mov r1, #FASTRAM_base ; (a.k.a. 00000000) 2701 0000196C E5D14046 ldrb r4, [r1, #interrupts_active - Mon_RAM_st art] 2702 00001970 E5D11047 ldrb r1, [r1, #interrupts_enable - Mon_RAM_st art] 2703 00001974 E0111004 ands r1, r1, r4 ; Z if no enabled interrupts 2704 00001978 01A0F00E moveq pc, lr ; No interrupts 2705 0000197C 2706 0000197C ; tst r0, #nIRQ_wire ; 2707 0000197C ; tsteq r12, #I_bit ; Interrupts enabled? 2708 0000197C ; movne pc, lr ; 2709 0000197C 2710 0000197C E28F1B01 E2811E36 adrl r1, IRQ_entry ; Point to appropriate ope ration 2711 00001984 E3A04083 mov r4, #State_running_IRQ ; 2712 00001988 E3180C02 tst r8, #Run_I_bit ; 2713 0000198C 1A000009 bne Int_procedure ; -Call- ISR 2714 00001990 2715 00001990 E5D7000C Int_normal ldrb r0, [r7, #arm_state - shared_variables] 2716 00001994 E3100080 tst r0, #&80 ; Running/stepping? 2717 00001998 01A0F00E moveq pc, lr ; No - so no action 2718 0000199C 2719 0000199C E1A0E003 mov lr, r3 ; `Return' address 2720 000019A0 E1A0F001 mov pc, r1 ; Appropriate action first 2721 000019A4 ARM Macro Assembler Page 85 2722 000019A4 E28F1B01 E2811FD1 enabled_FIQ adrl r1, FIQ_entry ; Point to appropriate ope ration 2723 000019AC E3A04084 mov r4, #State_running_FIQ ; 2724 000019B0 E3180C01 tst r8, #Run_F_bit ; 2725 000019B4 0AFFFFF5 beq Int_normal ; Retain operating state 2726 000019B8 2727 000019B8 EB000001 Int_procedure bl Save_state ; 2728 000019BC E24FE0F0 adr lr, Proc_loop2 ; Entry point in loop 2729 000019C0 E1A0F001 mov pc, r1 ; Appropriate action first 2730 000019C4 2731 000019C4 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2732 000019C4 ; Save state for leaving "procedure" {PC, SP, Mode, curr ent state} 2733 000019C4 ; Change to state R4 2734 000019C4 ; Corrupts R0, R2, R6 - must preserve R1 2735 000019C4 2736 000019C4 E3A06F55 Save_state mov r6, #exec_variables - Mon_RAM_start 2737 000019C8 E586B008 str r11, [r6, #run_until_PC - exec_variables ] 2738 000019CC 2739 000019CC E5990034 ldr r0, [r9, #sim_R13 - reg_block] 2740 000019D0 E586000C str r0, [r6, #run_until_SP - exec_variables] 2741 000019D4 2742 000019D4 E5D7000C ldrb r0, [r7, #arm_state - shared_variables] 2743 000019D8 E20C203F and r2, r12, #&3F ; Mode 2744 000019DC E1820400 orr r0, r2, r0, lsl #8 ; Hash together 2745 000019E0 E5860010 str r0, [r6, #run_until_mode - exec_variable s] 2746 000019E4 2747 000019E4 E5C7400C strb r4, [r7, #arm_state - shared_variables] 2748 000019E8 2749 000019E8 E1A0F00E mov pc, lr ; 2750 000019EC 2751 000019EC ;------------------------------------------------------- ----------------------- 2752 000019EC ; Fetch into R10 from R11 - post increment 2753 000019EC ; Check breakpoints, count instruction if `unbroken' 2754 000019EC ; Corrupts R0-R2 2755 000019EC 2756 000019EC E52DE004 fetch str lr, [sp, #-4]! ; Push return address 2757 000019F0 2758 000019F0 E3CBB003 bic r11, r11, #3 ; Align PC 2759 000019F4 E1A0200B mov r2, r11 ; PC 2760 000019F8 EBFFFDA6 bl read_memory_w ; Instruction fetch 2761 000019FC E1A0A001 mov r10, r1 ; Instruction register 2762 00001A00 2763 00001A00 E1D703D1 ldrsb r0, [r7, #break_enabled - shared_variabl es] 2764 00001A04 E3500000 cmp r0, #FALSE ; Test if breakpoints disabl ed 2765 00001A08 ; If equal then guaranteed C=1 ARM Macro Assembler Page 86 2766 00001A08 1B000221 blne breakpoint_check ; C=0 if breakpoint found 2767 00001A0C 349DF004 ldrcc pc, [sp], #4 ; So return 2768 00001A10 2769 00001A10 ; Copy breakpoints -should be enabled- flag to enabled p osition 2770 00001A10 E5D70030 ldrb r0, [r7, #break_enable - shared_variabl es] 2771 00001A14 E5C70031 strb r0, [r7, #break_enabled - shared_variabl es] 2772 00001A18 ; Always allows stepping of first instruction. 2773 00001A18 2774 00001A18 E28BB004 add r11, r11, #4 ; and increment 2775 00001A1C 2776 00001A1C E5970018 ldr r0, [r7, #arm_instr_count - shared_varia bles] 2777 00001A20 E2800001 add r0, r0, #1 ; Count instruction 2778 00001A24 E5870018 str r0, [r7, #arm_instr_count - shared_varia bles] 2779 00001A28 2780 00001A28 E49DF004 ldr pc, [sp], #4 ; Return 2781 00001A2C ; N.B. Carry still set if returning here 2782 00001A2C 2783 00001A2C ;------------------------------------------------------- ----------------------- 2784 00001A2C 2785 00001A2C E52DE004 step str lr, [sp, #-4]! ; Push return address 2786 00001A30 2787 00001A30 E1A00E2A mov r0, r10, lsr #28 ; Condition 2788 00001A34 E350000E cmp r0, #&0000000E ; Optimisation for "always" 2789 00001A38 1A00000A bne check_cc ; Return Z=1 for "go" 2790 00001A3C 2791 00001A3C E20A040E step_go and r0, r10, #&0E000000 ; Op. code 2792 00001A40 E79F0BA0 ldr r0, [pc, r0, lsr #23] ; N.B. no table offset 2793 00001A44 E08FF000 add pc, pc, r0 ; 2794 00001A48 2795 00001A48 00000074 DCD dp_reg - %f1 ; Relocatable jump table 2796 00001A4C 1 2797 00001A4C 000000A4 DCD dp_imm - %b1 ; Table could be halfword @ @@ 2798 00001A50 000003B0 DCD lsr_imm - %b1 ; one more instruction 2799 00001A54 000003A0 DCD lsr_reg - %b1 ; saves 3 words 2800 00001A58 00000538 DCD lsm - %b1 ; 2801 00001A5C 00000668 DCD branch - %b1 ; 2802 00001A60 00000690 DCD lsc - %b1 ; 2803 00001A64 00000680 DCD sys - %b1 ; 2804 00001A68 2805 00001A68 2806 00001A68 E28F1010 check_cc adr r1, cond_table ; 2807 00001A6C E7910100 ldr r0, [r1, r0, lsl #2] ; Get CC map (half) word 2808 00001A70 E1A01E2C mov r1, r12, lsr #28 ; Get flags 2809 00001A74 E1B00110 movs r0, r0, lsl r1 ; Select bit in map ARM Macro Assembler Page 87 2810 00001A78 5AFFFFEF bpl step_go ; 2811 00001A7C E49DF004 ldr pc, [sp], #4 ; Skip instruction - return 2812 00001A80 2813 00001A80 ; 0 bit for "go" in position indicated by flags from LH S 2814 00001A80 F0F00000 cond_table DCD &F0F00000 ; 0 - EQ Possibly compress? 2815 00001A84 0F0F0000 DCD &0F0F0000 ; 1 - NE @@@ 2816 00001A88 CCCC0000 DCD &CCCC0000 ; 2 - CS Not too time 2817 00001A8C 33330000 DCD &33330000 ; 3 - CC critical 2818 00001A90 FF000000 DCD &FF000000 ; 4 - MI AL trapped 1st 2819 00001A94 00FF0000 DCD &00FF0000 ; 5 - PL 2820 00001A98 AAAA0000 DCD &AAAA0000 ; 6 - VS 2821 00001A9C 55550000 DCD &55550000 ; 7 - VC 2822 00001AA0 CFCF0000 DCD &CFCF0000 ; 8 - HI 2823 00001AA4 30300000 DCD &30300000 ; 9 - LS 2824 00001AA8 55AA0000 DCD &55AA0000 ; A - GE 2825 00001AAC AA550000 DCD &AA550000 ; B - LT 2826 00001AB0 5FAF0000 DCD &5FAF0000 ; C - GT 2827 00001AB4 A0500000 DCD &A0500000 ; D - LE 2828 00001AB8 00000000 DCD &00000000 ; E - AL 2829 00001ABC FFFF0000 DCD &FFFF0000 ; F - NV 2830 00001AC0 2831 00001AC0 ; Untried ** NEW CODE ** @@@ 2832 00001AC0 ; adr r1, cond_table ; +2 instr. -6 words @@@ 2833 00001AC0 ; mov r0, r0, lsl #1 ; Can go too if R0 sorted earlier 2834 00001AC0 ; ldrh r0, [r1, r0] ; ^^^ MAYBE! - LSB MASK ??? 2835 00001AC0 ; mov r0, r0, lsl #16 ; 2836 00001AC0 ; mov r1, r12, lsr #28 ; Get flags ... etc. 2837 00001AC0 2838 00001AC0 ;------------------------------------------------------- ----------------------- 2839 00001AC0 2840 00001AC0 E20A0090 dp_reg and r0, r10, #&00000090 ; MUL, SWP, LSRH, etc. 2841 00001AC4 E3500090 cmp r0, #&00000090 ; Extension? 2842 00001AC8 0A000053 beq dp_reg_ext_A ; 2843 00001ACC 2844 00001ACC E20A0619 and r0, r10, #&01900000 ; MSR/MRS, etc. 2845 00001AD0 E3500401 cmp r0, #&01000000 ; Extension? 2846 00001AD4 0A000081 beq dp_reg_ext_B ; 2847 00001AD8 2848 00001AD8 E20A680F and r6, r10, #&000F0000 ; Rn 2849 00001ADC E356080F cmp r6, #&000F0000 ; Test for PC 2850 00001AE0 17996726 ldrne r6, [r9, r6, lsr #14] ; Current register map 2851 00001AE4 028B6004 addeq r6, r11, #4 ; or PC 2852 00001AE8 2853 00001AE8 E28FE020 adr lr, dp_all ; Return to other dp ops. 2854 00001AEC EA0001B5 b shifted_Rm ; Shifter_carry_out in CF 2855 00001AF0 2856 00001AF0 E20A0619 dp_imm and r0, r10, #&01900000 ; 2857 00001AF4 E3500401 cmp r0, #&01000000 ; Extension? 2858 00001AF8 0A000086 beq dp_imm_ext ; ARM Macro Assembler Page 88 2859 00001AFC 2860 00001AFC E20A680F and r6, r10, #&000F0000 ; Rn 2861 00001B00 E356080F cmp r6, #&000F0000 ; Test for PC 2862 00001B04 17996726 ldrne r6, [r9, r6, lsr #14] ; Current register map 2863 00001B08 028B6004 addeq r6, r11, #4 ; or PC 2864 00001B0C 2865 00001B0C EB0001D0 bl immediate ; Into R1 (also sets up CF) 2866 00001B10 2867 00001B10 E20A061E dp_all and r0, r10, #&01E00000 ; Operation (shifter _carry_out in CF) 2868 00001B14 E7DF0AA0 ldrb r0, [pc, r0, lsr #21] ; N.B. no table offset 2869 00001B18 E08FF100 add pc, pc, r0, lsl #2 ; 2870 00001B1C 2871 00001B1C 28 DCB (dp_and - %f1) / 4 ; 0 2872 00001B1D 23 DCB (dp_eor - %f1) / 4 ; 1 2873 00001B1E 05 DCB (dp_sub - %f1) / 4 ; 2 2874 00001B1F 09 DCB (dp_rsb - %f1) / 4 ; 3 2875 00001B20 1 2876 00001B20 0D DCB (dp_add - %b1) / 4 ; 4 2877 00001B21 0B DCB (dp_adc - %b1) / 4 ; 5 2878 00001B22 03 DCB (dp_sbc - %b1) / 4 ; 6 2879 00001B23 07 DCB (dp_rsc - %b1) / 4 ; 7 2880 00001B24 1B DCB (dp_tst - %b1) / 4 ; 8 2881 00001B25 19 DCB (dp_teq - %b1) / 4 ; 9 2882 00001B26 20 DCB (dp_cmp - %b1) / 4 ; A 2883 00001B27 1E DCB (dp_cmn - %b1) / 4 ; B 2884 00001B28 25 DCB (dp_orr - %b1) / 4 ; C 2885 00001B29 2B DCB (dp_mov - %b1) / 4 ; D 2886 00001B2A 27 DCB (dp_bic - %b1) / 4 ; E 2887 00001B2B 2A DCB (dp_mvn - %b1) / 4 ; F 2888 00001B2C 2889 00001B2C E31C0202 dp_sbc tst r12, #Cflag ; 2890 00001B30 02466001 subeq r6, r6, #1 ; fall into ... 2891 00001B34 2892 00001B34 E0561001 dp_sub subs r1, r6, r1 ; 2893 00001B38 EA000006 b dp_arith_out ; 2894 00001B3C 2895 00001B3C E31C0202 dp_rsc tst r12, #Cflag ; 2896 00001B40 02411001 subeq r1, r1, #1 ; fall into ... 2897 00001B44 2898 00001B44 E0511006 dp_rsb subs r1, r1, r6 ; 2899 00001B48 EA000002 b dp_arith_out ; 2900 00001B4C 2901 00001B4C E31C0202 dp_adc tst r12, #Cflag ; 2902 00001B50 12866001 addne r6, r6, #1 ; fall into ... 2903 00001B54 2904 00001B54 E0961001 dp_add adds r1, r6, r1 ; 2905 00001B58 E10F2000 dp_arith_out mrs r2, cpsr ; Keep the flags ARM Macro Assembler Page 89 2906 00001B5C EB0001C7 bl write_reg ; 2907 00001B60 E31A0601 tst r10, #Sbit ; 2908 00001B64 049DF004 ldreq pc, [sp], #4 ; Return no flag alteration 2909 00001B68 E20A0A0F and r0, r10, #&0000F000 ; Rd field 2910 00001B6C E3500A0F cmp r0, #&0000F000 ; Destination = PC? 2911 00001B70 0A000021 beq spsr_copy_up ; 2912 00001B74 E202220F dp_arith_out1 and r2, r2, #&F0000000 ; All the flags for adds 2913 00001B78 E3CCC20F bic r12, r12, #&F0000000 ; 2914 00001B7C E18CC002 orr r12, r12, r2 ; 2915 00001B80 E49DF004 ldr pc, [sp], #4 ; Return 2916 00001B84 2917 00001B84 E1360001 dp_teq teq r6, r1 ; Note: shifter carry set up 2918 00001B88 EA000000 b dp_tst1 ; Forgivable inefficiency 2919 00001B8C 2920 00001B8C E1160001 dp_tst tst r6, r1 ; Note: shifter carry set up 2921 00001B90 E10F2000 dp_tst1 mrs r2, cpsr ; Keep the flags 2922 00001B94 EA000014 b dp_logical_out1 ; Slower, but shorter 2923 00001B98 2924 00001B98 ; and r2, r2, #&E0000000 ; Not the overflow flag 2925 00001B98 ; bic r12, r12, #&E0000000 ; 2926 00001B98 ; orr r12, r12, r2 ; 2927 00001B98 ; ldr pc, [sp], #4 ; Return 2928 00001B98 2929 00001B98 E1760001 dp_cmn cmn r6, r1 ; 2930 00001B9C EA000000 b dp_cmp1 ; 2931 00001BA0 2932 00001BA0 ;dp_cmn rsb r1, r1, #0 ; 2's complement R1 and fall in to 2933 00001BA0 ; The previous line doesn't work; Carry is wrong if R1=0 2934 00001BA0 2935 00001BA0 E1560001 dp_cmp cmp r6, r1 ; 2936 00001BA4 E10F2000 dp_cmp1 mrs r2, cpsr ; Get the flags 2937 00001BA8 EAFFFFF1 b dp_arith_out1 ; Slower, but shorter 2938 00001BAC 2939 00001BAC ; and r2, r2, #&F0000000 ; Use all the flags 2940 00001BAC ; bic r12, r12, #&F0000000 ; 2941 00001BAC ; orr r12, r12, r2 ; 2942 00001BAC ; ldr pc, [sp], #4 ; Return 2943 00001BAC 2944 00001BAC 2945 00001BAC E0361001 dp_eor eors r1, r6, r1 ; Note: shifter carry set up 2946 00001BB0 EA000006 b dp_logical_out ; 2947 00001BB4 2948 00001BB4 E1961001 ARM Macro Assembler Page 90 dp_orr orrs r1, r6, r1 ; Note: shifter carry set up 2949 00001BB8 EA000004 b dp_logical_out ; 2950 00001BBC 2951 00001BBC E1E01001 dp_bic mvn r1, r1 ; Note: shifter carry set up 2952 00001BC0 E0161001 dp_and ands r1, r6, r1 ; Note: shifter carry set up 2953 00001BC4 EA000001 b dp_logical_out ; 2954 00001BC8 2955 00001BC8 E1E01001 dp_mvn mvn r1, r1 ; Note: shifter carry set up 2956 00001BCC E1B01001 dp_mov movs r1, r1 ; Note: shifter carry set up 2957 00001BD0 E10F2000 dp_logical_out mrs r2, cpsr ; Keep the flags 2958 00001BD4 EB0001A9 bl write_reg ; 2959 00001BD8 E31A0601 tst r10, #Sbit ; 2960 00001BDC 049DF004 ldreq pc, [sp], #4 ; Return no flag alteration 2961 00001BE0 E20A0A0F and r0, r10, #&0000F000 ; Rd field 2962 00001BE4 E3500A0F cmp r0, #&0000F000 ; Destination = PC? 2963 00001BE8 0A000003 beq spsr_copy_up ; 2964 00001BEC E202220E dp_logical_out1 and r2, r2, #&E0000000 ; Not the overflow flag 2965 00001BF0 E3CCC20E bic r12, r12, #&E0000000 ; 2966 00001BF4 E18CC002 orr r12, r12, r2 ; 2967 00001BF8 E49DF004 ldr pc, [sp], #4 ; Return 2968 00001BFC 2969 00001BFC ; The following is branched to and finishes by "returnin g" 2970 00001BFC E589C0A8 spsr_copy_up str r12, [r9, #sim_CPSR - reg_block] 2971 00001C00 ; CPSR into dustbin as default 2972 00001C00 EB000071 bl find_spsr ; 2973 00001C04 2974 00001C04 E20C200F and r2, r12, #&F ; Old mode 2975 00001C08 E799C100 ldr r12, [r9, r0, lsl #2] ; Load CPSR 2976 00001C0C E1A00002 mov r0, r2 ; Register allocation poor : -( 2977 00001C10 E20C100F and r1, r12, #&F ; New mode 2978 00001C14 2979 00001C14 E49DE004 ldr lr, [sp], #4 ; Pop return address 2980 00001C18 EA00014A b mode_reg_swap ; Update register cache & ret. 2981 00001C1C 2982 00001C1C ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2983 00001C1C ; Instruction set extensions et alia 2984 00001C1C 2985 00001C1C E31A0060 ARM Macro Assembler Page 91 dp_reg_ext_A tst r10, #&00000060 ; Half-word transfer? 2986 00001C20 1A000098 bne lsrh ; 2987 00001C24 2988 00001C24 E20A1507 and r1, r10, #&01C00000 ; 2989 00001C28 E1A01AA1 mov r1, r1, lsr #21 ; 2990 00001C2C E19F00B1 ldrh r0, [pc, r1] ; Just a jump table 2991 00001C30 E08FF000 add pc, pc, r0 ; 2992 00001C34 2993 00001C34 0C 00 DCW dp_mul - %f1 ; 2994 00001C36 A4 04 DCW undef - %f1 ; 2995 00001C38 1 2996 00001C38 0C 00 DCW dp_umull - %b1 ; 2997 00001C3A 0C 00 DCW dp_smull - %b1 ; 2998 00001C3C 14 03 DCW swap - %b1 ; 2999 00001C3E 14 03 DCW swapb - %b1 ; 3000 00001C40 A4 04 DCW undef - %b1 ; 3001 00001C42 A4 04 DCW undef - %b1 ; 3002 00001C44 ALIGN 3003 00001C44 3004 00001C44 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 3005 00001C44 3006 00001C44 dp_mul 3007 00001C44 dp_umull 3008 00001C44 E20A000F dp_smull and r0, r10, #&F ; All multiplies 3009 00001C48 EB000187 bl read_reg ; 3010 00001C4C E1A03000 mov r3, r0 ; Rm 3011 00001C50 E1A0042A mov r0, r10, lsr #8 ; 3012 00001C54 EB000184 bl read_reg ; 3013 00001C58 E1A04000 mov r4, r0 ; Rs 3014 00001C5C 3015 00001C5C E31A0502 tst r10, #MUL_L_bit ; 3016 00001C60 03A0000C moveq r0, #12 ; Source register position " Rn" 3017 00001C64 13A00010 movne r0, #16 ; Ditto for RdHi 3018 00001C68 3019 00001C68 E31A0602 tst r10, #MUL_A_bit ; 3020 00001C6C 03A00000 moveq r0, #0 ; Accumulate nothing 3021 00001C70 11A0003A movne r0, r10, lsr r0 ; or something 3022 00001C74 1B00017C blne read_reg ; 3023 00001C78 E1A01000 mov r1, r0 ; "Rn" or RdHi 3024 00001C7C 3025 00001C7C E31A0502 tst r10, #MUL_L_bit ; 3026 00001C80 0A00000B beq dp_mul_short ; 3027 00001C84 3028 00001C84 E31A0602 tst r10, #MUL_A_bit ; Refresh condition 3029 00001C88 03A00000 moveq r0, #0 ; Accumulate nothing 3030 00001C8C 11A0082A movne r0, r10, lsr #16 ; or something 3031 00001C90 1B000175 blne read_reg ; RdLo 3032 00001C94 3033 00001C94 E31A0501 tst r10, #MUL_U_bit ; Signed? 3034 00001C98 00B10493 umlaleqs r0, r1, r3, r4 ; 3035 00001C9C 10F10493 smlalnes r0, r1, r3, r4 ; 3036 00001CA0 E10F2000 mrs r2, cpsr ; Keep the flags ARM Macro Assembler Page 92 3037 00001CA4 3038 00001CA4 E20A4A0F and r4, r10, #&0000F000 ; RdLo 3039 00001CA8 E3540A0F cmp r4, #&0000F000 ; Test for PC 3040 00001CAC 17890520 strne r0, [r9, r0, lsr #10] ; Current register map 3041 00001CB0 ; not needed moveq r11, r0 ; or PC 3042 00001CB0 EA000001 b dp_mul_out ; Rejoin at this address 3043 00001CB4 3044 00001CB4 E0311493 dp_mul_short mlas r1, r3, r4, r1 ; Short mult. is simpler! 3045 00001CB8 E10F2000 mrs r2, cpsr ; Keep the flags 3046 00001CBC 3047 00001CBC E20A080F dp_mul_out and r0, r10, #&000F0000 ; "Rd" or RdHi 3048 00001CC0 E350080F cmp r0, #&000F0000 ; Test for PC 3049 00001CC4 17891720 strne r1, [r9, r0, lsr #14] ; Current register map 3050 00001CC8 ; not needed moveq r11, r1 ; or PC 3051 00001CC8 3052 00001CC8 E31A0601 tst r10, #Sbit ; 3053 00001CCC 049DF004 ldreq pc, [sp], #4 ; Return no flag alteration 3054 00001CD0 3055 00001CD0 E2022103 and r2, r2, #&C0000000 ; Not C or V 3056 00001CD4 E3CCC103 bic r12, r12, #&C0000000 ; 3057 00001CD8 E18CC002 orr r12, r12, r2 ; 3058 00001CDC E49DF004 ldr pc, [sp], #4 ; Return 3059 00001CE0 3060 00001CE0 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 3061 00001CE0 3062 00001CE0 E31A0602 dp_reg_ext_B tst r10, #&00200000 ; MSR/MSR ... 3063 00001CE4 0A00000F beq dp_mrs ; 3064 00001CE8 E31A0010 tst r10, #&00000010 ; 3065 00001CEC 0A000014 beq dp_msr ; 3066 00001CF0 3067 00001CF0 ; X1 0x10 XXX xxx1 X 3068 00001CF0 E3CA02FF bic r0, r10, #&F000000F ; 3069 00001CF4 E59F1018 ldr r1, BX_value ; 3070 00001CF8 E1500001 cmp r0, r1 ; 3071 00001CFC 1A0000F6 bne undef ; 3072 00001D00 3073 00001D00 E20A000F and r0, r10, #&0F ; 3074 00001D04 EB000158 bl read_reg ; 3075 00001D08 E3C1B001 bic r11, r1, #1 ; Reult into PC 3076 00001D0C E3100001 tst r0, #1 ; Thumb bit? 3077 00001D10 ; @@@ orrne r12, r12, T_bit ; Yes, switch mode 3078 00001D10 3079 00001D10 E49DF004 ldr pc, [sp], #4 ; Return 3080 00001D14 3081 00001D14 012FFF10 BX_value DCD &012FFF10 ; BX instruction 3082 00001D18 ARM Macro Assembler Page 93 3083 00001D18 3084 00001D18 3085 00001D18 E31A0602 dp_imm_ext tst r10, #&00200000 ; 3086 00001D1C 0A0000EE beq undef ; Could test bits 15..12 als o 3087 00001D20 E28FE028 adr lr, dp_msr1 ; 3088 00001D24 EA00014A b immediate ; Value into R1 3089 00001D28 3090 00001D28 3091 00001D28 E31A0501 dp_mrs tst r10, #Rbit ; 3092 00001D2C 01A0100C moveq r1, r12 ; CPSR 3093 00001D30 1B000025 blne find_spsr ; Flags preserved 3094 00001D34 17991100 ldrne r1, [r9, r0, lsl #2] ; Get SPSR 3095 00001D38 3096 00001D38 E49DE004 ldr lr, [sp], #4 ; Pop return address 3097 00001D3C EA00014F b write_reg ; and leave 3098 00001D40 3099 00001D40 3100 00001D40 F00000FF PSR_valid_bits DCD &F00000FF ; Implemented bits in PSRs 3101 00001D44 3102 00001D44 E20A000F dp_msr and r0, r10, #&F ; Register specifier 3103 00001D48 EB000147 bl read_reg ; Value returned in R0 3104 00001D4C E1A01000 mov r1, r0 ; 3105 00001D50 3106 00001D50 E51F0018 dp_msr1 ldr r0, PSR_valid_bits ; See just above 3107 00001D54 E0011000 and r1, r1, r0 ; Mask for possible bits onl y 3108 00001D58 3109 00001D58 E31A0501 tst r10, #Rbit ; 3110 00001D5C 1A00000E bne dp_msr_spsr ; Work with an SPSR 3111 00001D60 3112 00001D60 E31A0702 tst r10, #&00080000 ; Flags? 3113 00001D64 13CCC4FF bicne r12, r12, #&FF000000 ; Yes, lose old flags 3114 00001D68 03C114FF biceq r1, r1, #&FF000000 ; No, lose new bits 3115 00001D6C E31A0801 tst r10, #&00010000 ; Status? 3116 00001D70 131C000F tstne r12, #&F ; If yes, see if privileged 3117 00001D74 1A000002 bne msr_status ; Yup, that too! 3118 00001D78 3119 00001D78 E3C110FF bic r1, r1, #&FF ; No status change 3120 00001D7C E18CC001 orr r12, r12, r1 ; 3121 00001D80 E49DF004 ldr pc, [sp], #4 ; Return 3122 00001D84 3123 00001D84 E20C000F msr_status and r0, r12, #&F ; Remember old mode 3124 00001D88 E3CCC0FF bic r12, r12, #&000000FF ; but lose in CPSR 3125 00001D8C E18CC001 orr r12, r12, r1 ; Insert new status 3126 00001D90 E201100F and r1, r1, #&F ; Recover new mode 3127 00001D94 E49DE004 ldr lr, [sp], #4 ; Pop return address 3128 00001D98 EA0000EA b mode_reg_swap ; Update register cache ARM Macro Assembler Page 94 3129 00001D9C 3130 00001D9C 3131 00001D9C E1A02001 dp_msr_spsr mov r2, r1 ; 3132 00001DA0 EB000009 bl find_spsr ; Corrupts R0, R1 3133 00001DA4 E7993100 ldr r3, [r9, r0, lsl #2] ; Get SPSR 3134 00001DA8 3135 00001DA8 E31A0702 tst r10, #&00080000 ; Flags? 3136 00001DAC 13C334FF bicne r3, r3, #&FF000000 ; Yes, lose old flags 3137 00001DB0 03C224FF biceq r2, r2, #&FF000000 ; No, lose new bits 3138 00001DB4 3139 00001DB4 E31A0801 tst r10, #&00010000 ; Status? 3140 00001DB8 13C330FF bicne r3, r3, #&FF ; Lose old status 3141 00001DBC 03C220FF biceq r2, r2, #&FF ; No status change 3142 00001DC0 3143 00001DC0 E1833002 orr r3, r3, r2 ; 3144 00001DC4 E7893100 str r3, [r9, r0, lsl #2] ; Save SPSR 3145 00001DC8 E49DF004 ldr pc, [sp], #4 ; Return 3146 00001DCC 3147 00001DCC ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 3148 00001DCC 3149 00001DCC E20C000F find_spsr and r0, r12, #&F ; R0 := 1/4 offset to SPSR 3150 00001DD0 E28F1004 adr r1, spsr_tab ; 3151 00001DD4 E7D10000 ldrb r0, [r1, r0] ; 3152 00001DD8 E1A0F00E mov pc, lr ; 3153 00001DDC 3154 00001DDC ; Positions of SPSRs (sim_CPSR - reg_block)/4 = 'dustbi n' 3155 00001DDC 2A 29 spsr_tab DCB (sim_CPSR - reg_block)/4, (sim_SPSR_fiq - reg_block)/4 3156 00001DDE 28 25 DCB (sim_SPSR_irq - reg_block)/4, (sim_SPSR_ svc - reg_block)/4 3157 00001DE0 2A 2A DCB (sim_CPSR - reg_block)/4, (sim_CPSR - re g_block)/4 3158 00001DE2 2A 26 DCB (sim_CPSR - reg_block)/4, (sim_SPSR_abt - reg_block)/4 3159 00001DE4 2A 2A DCB (sim_CPSR - reg_block)/4, (sim_CPSR - re g_block)/4 3160 00001DE6 2A 27 DCB (sim_CPSR - reg_block)/4, (sim_SPSR_unde f - reg_block)/4 3161 00001DE8 2A 2A DCB (sim_CPSR - reg_block)/4, (sim_CPSR - re g_block)/4 3162 00001DEA 2A 2A DCB (sim_CPSR - reg_block)/4, (sim_CPSR - re g_block)/4 3163 00001DEC 3164 00001DEC ALIGN 3165 00001DEC 3166 00001DEC ;------------------------------------------------------- ----------------------- 3167 00001DEC 3168 00001DEC E31A0010 lsr_reg tst r10, #&00000010 ; Test for undefined 3169 00001DF0 1A0000B9 bne undef ; Undefined ARM Macro Assembler Page 95 3170 00001DF4 3171 00001DF4 E28FE008 adr lr, lsr_all ; Set return address 3172 00001DF8 EA0000F2 b shifted_Rm ; Offset in R1 3173 00001DFC 3174 00001DFC 3175 00001DFC E1A01A0A lsr_imm mov r1, r10, lsl #20 ; Lose all but offset 3176 00001E00 E1A01A21 mov r1, r1, lsr #20 ; 3177 00001E04 3178 00001E04 E20A080F lsr_all and r0, r10, #&000F0000 ; R2 := base register 3179 00001E08 E350080F cmp r0, #&000F0000 ; Test for PC 3180 00001E0C 17992720 ldrne r2, [r9, r0, lsr #14] ; Current register map 3181 00001E10 028B2004 addeq r2, r11, #4 ; or PC 3182 00001E14 3183 00001E14 E31A0502 tst r10, #Ubit ; 3184 00001E18 10823001 addne r3, r2, r1 ; Up ... 3185 00001E1C 00423001 subeq r3, r2, r1 ; ... or down 3186 00001E20 3187 00001E20 E1B01CEA movs r1, r10, ror #25 ; P bit into carry (R1 is scrap) 3188 00001E24 ; Guaranteed non-zero (ZF=0) 3189 00001E24 21A02003 movcs r2, r3 ; Pre-index; R2 now address 3190 00001E28 231A0602 tstcs r10, #Wbit ; ZF=1 if no writeback 3191 00001E2C ; CS => only if pre-indexed 3192 00001E2C 0A000001 beq lsr_imm1 ; No writeback 3193 00001E30 3194 00001E30 E350080F cmp r0, #&000F0000 ; R0 -> Rn (still) 3195 00001E34 17893720 strne r3, [r9, r0, lsr #14] ; Current register map 3196 00001E38 ; not needed moveq r11, r3 ; or PC 3197 00001E38 3198 00001E38 E31A0501 lsr_imm1 tst r10, #Bbit ; 3199 00001E3C 1A000008 bne lsr_byte ; 3200 00001E40 3201 00001E40 E31A0601 tst r10, #Ldbit ; 3202 00001E44 1A000003 bne lsr_imm_ldr ; 3203 00001E48 3204 00001E48 E1A0062A mov r0, r10, lsr #12 ; 3205 00001E4C EB000106 bl read_reg ; 3206 00001E50 E49DE004 ldr lr, [sp], #4 ; Return address 3207 00001E54 EAFFFD26 b write_memory_w ; Data store 3208 00001E58 3209 00001E58 3210 00001E58 EBFFFC8E lsr_imm_ldr bl read_memory_w ; Data load 3211 00001E5C E49DE004 ldr lr, [sp], #4 ; Pop return address 3212 00001E60 EA000106 b write_reg ; and depart 3213 00001E64 3214 00001E64 3215 00001E64 E31A0601 lsr_byte tst r10, #Ldbit ; 3216 00001E68 1A000003 bne lsr_imm_ldrb ; ARM Macro Assembler Page 96 3217 00001E6C 3218 00001E6C E1A0062A mov r0, r10, lsr #12 ; STRB code 3219 00001E70 EB0000FD bl read_reg ; 3220 00001E74 ; cmp r2, #tube ; @@@ 3221 00001E74 ; beq tube_out 3222 00001E74 ; cmp r2, #tube_too 3223 00001E74 ; beq Wr_IO_Tube ; 3224 00001E74 3225 00001E74 E49DE004 ldr lr, [sp], #4 ; Return address 3226 00001E78 EAFFFD38 b write_memory_b ; Data write 3227 00001E7C 3228 00001E7C EBFFFC9E lsr_imm_ldrb bl read_memory_b ; Data load 3229 00001E80 E49DE004 ldr lr, [sp], #4 ; Pop return address 3230 00001E84 EA0000FD b write_reg ; 3231 00001E88 3232 00001E88 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 3233 00001E88 3234 00001E88 E31A0501 lsrh tst r10, #&00400000 ; Immediate offset? 3235 00001E8C 1A000002 bne lsrh_imm ; 3236 00001E90 E1A0000A mov r0, r10 ; 3237 00001E94 E28FE00C adr lr, lsrh_all ; Call with different retur n addr 3238 00001E98 EA0000F3 b read_reg ; More efficient! 3239 00001E9C 3240 00001E9C E3CA00F0 lsrh_imm bic r0, r10, #&F0 ; 3241 00001EA0 E1800220 orr r0, r0, r0, lsr #4 ; Assemble offset 3242 00001EA4 E20000FF and r0, r0, #&FF ; R0 := immediate offset 3243 00001EA8 3244 00001EA8 E20A180F lsrh_all and r1, r10, #&000F0000 ; R1 := base register 3245 00001EAC E351080F cmp r1, #&000F0000 ; Test for PC 3246 00001EB0 17992721 ldrne r2, [r9, r1, lsr #14] ; Current register map 3247 00001EB4 028B2004 addeq r2, r11, #4 ; or PC 3248 00001EB8 3249 00001EB8 E31A0502 tst r10, #Ubit ; Set R3 to indexed value 3250 00001EBC 10823000 addne r3, r2, r0 ; Up ... 3251 00001EC0 00423000 subeq r3, r2, r0 ; ... or down 3252 00001EC4 3253 00001EC4 E1B00CEA movs r0, r10, ror #25 ; P bit into carry (R0 is scrap) 3254 00001EC8 ; Guaranteed non-zero (ZF=0) 3255 00001EC8 21A02003 movcs r2, r3 ; Pre-index; R2 now address 3256 00001ECC 231A0602 tstcs r10, #Wbit ; ZF=1 if no writeback 3257 00001ED0 ; CS => only if pre-indexed 3258 00001ED0 0A000001 beq lsrh1 ; No writeback 3259 00001ED4 3260 00001ED4 E351080F cmp r1, #&000F0000 ; R1 -> Rn (still) 3261 00001ED8 17893721 strne r3, [r9, r1, lsr #14] ; Current register map 3262 00001EDC ; not needed moveq r11, r3 ; or PC ARM Macro Assembler Page 97 3263 00001EDC 3264 00001EDC E31A0601 lsrh1 tst r10, #Ldbit ; 3265 00001EE0 0A000012 beq strh_code ; 3266 00001EE4 3267 00001EE4 E21A0060 ands r0, r10, #&00000060 ; SH bits 3268 00001EE8 0A00007B beq undef ; Really already broken, @ @@ 3269 00001EEC ; but impossible to reach anyway 3270 00001EEC E3500040 cmp r0, #&00000040 ; Middle of three values 3271 00001EF0 3A000001 blo ldrh_start ; 00000020 3272 00001EF4 0A000003 beq ldrsb_start ; 00000040 3273 00001EF8 EA000007 b ldrsh_start ; 00000060 3274 00001EFC ; RETEST PENDING @@@ 3275 00001EFC 3276 00001EFC ; old stuff ldr r1, [pc, r0, lsr #3] ; 3277 00001EFC ; add pc, pc, r1 ; 3278 00001EFC ; 3279 00001EFC ; DCD undef - %f1 ; Really already broken, 3280 00001EFC ;1 ; but impossible to reach anyway 3281 00001EFC ; DCD ldrh_start - %b1 ; 3282 00001EFC ; DCD ldrsb_start - %b1 ; 3283 00001EFC ; DCD ldrsh_start - %b1 ; 3284 00001EFC 3285 00001EFC 3286 00001EFC EBFFFC6E ldrh_start bl read_memory_h ; Data fetch (zero extended) 3287 00001F00 E49DE004 ldr lr, [sp], #4 ; Recover return address 3288 00001F04 EA0000DD b write_reg ; Write and exit 3289 00001F08 3290 00001F08 3291 00001F08 EBFFFC7B ldrsb_start bl read_memory_b ; Data fetch 3292 00001F0C E1A01C01 mov r1, r1, lsl #24 ; Sign extend 3293 00001F10 E1A01C41 mov r1, r1, asr #24 ; 3294 00001F14 E49DE004 ldr lr, [sp], #4 ; Recover return address 3295 00001F18 EA0000D8 b write_reg ; Write and exit 3296 00001F1C 3297 00001F1C 3298 00001F1C EBFFFC66 ldrsh_start bl read_memory_h ; Data fetch 3299 00001F20 E1A01801 mov r1, r1, lsl #16 ; Sign extend 3300 00001F24 E1A01841 mov r1, r1, asr #16 ; 3301 00001F28 E49DE004 ldr lr, [sp], #4 ; Recover return address 3302 00001F2C EA0000D3 b write_reg ; Write and exit 3303 00001F30 3304 00001F30 3305 00001F30 E20A0060 strh_code and r0, r10, #&00000060 ; SH bits 3306 00001F34 E3500020 cmp r0, #&00000020 ; Only legal pattern 3307 00001F38 1A000067 bne undef ; else fall into ... 3308 00001F3C 3309 00001F3C ; ldr r0, [pc, r0, lsr #3] ; ARM Macro Assembler Page 98 3310 00001F3C ; add pc, pc, r0 ; 3311 00001F3C ; 3312 00001F3C ; DCD undef - %f1 ; Really already broken, 3313 00001F3C ;1 ; but impossible to reach anyway 3314 00001F3C ; DCD strh_start - %b1 ; 3315 00001F3C ; DCD undef - %b1 ; Possible and should be trapped @@@ 3316 00001F3C ; DCD undef - %b1 ; Possible and should be trapped @@@ 3317 00001F3C 3318 00001F3C ;strh_start 3319 00001F3C E1A0062A mov r0, r10, lsr #12 ; 3320 00001F40 EB0000C9 bl read_reg ; 3321 00001F44 E49DE004 ldr lr, [sp], #4 ; Recover return address 3322 00001F48 EAFFFCF3 b write_memory_h ; Write and return 3323 00001F4C ; Could jump 1 instr. into "write_memory_h", but even le ss structured! 3324 00001F4C 3325 00001F4C ;------------------------------------------------------- ----------------------- 3326 00001F4C 3327 00001F4C swapb 3328 00001F4C E1A0082A swap mov r0, r10, lsr #16 ; 3329 00001F50 EB0000C5 bl read_reg ; 3330 00001F54 E1A02000 mov r2, r0 ; R2 := address 3331 00001F58 E1A0000A mov r0, r10 ; 3332 00001F5C EB0000C2 bl read_reg ; R0 := store data 3333 00001F60 3334 00001F60 E31A0501 tst r10, #Bbit ; Size appropriately 3335 00001F64 1A000002 bne swap_byte ; 3336 00001F68 3337 00001F68 EBFFFC4A bl read_memory_w ; 3338 00001F6C EBFFFCE0 bl write_memory_w ; 3339 00001F70 EA000001 b swap1 ; 3340 00001F74 3341 00001F74 EBFFFC60 swap_byte bl read_memory_b ; 3342 00001F78 EBFFFCF8 bl write_memory_b ; 3343 00001F7C 3344 00001F7C E49DE004 swap1 ldr lr, [sp], #4 ; Return address 3345 00001F80 EA0000BE b write_reg ; Rd := R1 3346 00001F84 3347 00001F84 ;------------------------------------------------------- ----------------------- 3348 00001F84 ; N.B. This performs memory cycles in either direction 3349 00001F84 ; Not set up to handle data aborts 3350 00001F84 3351 00001F84 E1A0082A lsm mov r0, r10, lsr #16 ; Fetch Rn 3352 00001F88 EB0000B7 bl read_reg ; 3353 00001F8C E1A05000 mov r5, r0 ; Keep original value 3354 00001F90 E3C02003 bic r2, r0, #3 ; and lose lowest bits here 3355 00001F94 3356 00001F94 E3A03000 mov r3, #0 ; Accumulator 3357 00001F98 E1A0680A mov r6, r10, lsl #16 ; Get bitmask ARM Macro Assembler Page 99 3358 00001F9C E1A04826 mov r4, r6, lsr #16 ; Also keep a copy 3359 00001FA0 3360 00001FA0 E1B06086 lsm_ngen movs r6, r6, lsl #1 ; Shift out each bit 3361 00001FA4 E2A33000 adc r3, r3, #0 ; adding into accumulator 3362 00001FA8 1AFFFFFC bne lsm_ngen ; until all bits gone 3363 00001FAC 3364 00001FAC E31A0502 tst r10, #Ubit ; 3365 00001FB0 00422103 subeq r2, r2, r3, lsl #2 ; If decrement mode 3366 00001FB4 E02A008A eor r0, r10, r10, lsl #1 ; 3367 00001FB8 E3100401 tst r0, #&01000000 ; "DA" or "IB"? 3368 00001FBC 02822004 addeq r2, r2, #4 ; Base addess 3369 00001FC0 3370 00001FC0 E3C44902 bic r4, r4, #LSM_PC_bit ; Leave out PC 3371 00001FC4 E1A06009 mov r6, r9 ; Pointer to r0 3372 00001FC8 3373 00001FC8 3374 00001FC8 E3E00000 mov r0, #-1 ; (Illegal) offset of regist er bank break 3375 00001FCC E31A0501 tst r10, #LSM_S_bit ; or R12 + #4 & R13 3376 00001FD0 1A00002D bne lsm_hat ; S bit set - off main flow 3377 00001FD4 ; lsm_hat will indicate where (if anywhere) the paged re gisters start (i.e. R8 or R13) 3378 00001FD4 3379 00001FD4 E31A0601 lsm_1 tst r10, #Ldbit ; Reentry after "^" checks 3380 00001FD8 1A00000F bne ldm_loop ; Load 3381 00001FDC E1A01000 mov r1, r0 ; Store - uses different reg . 3382 00001FE0 ; and fall into ... 3383 00001FE0 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 3384 00001FE0 3385 00001FE0 E1B040A4 stm_loop movs r4, r4, lsr #1 ; Next bit in reg. list 3386 00001FE4 3A000002 bcc stm_1 ; clear 3387 00001FE8 3388 00001FE8 E5960000 ldr r0, [r6] ; Read register value 3389 00001FEC EBFFFCC0 bl write_memory_w ; 3390 00001FF0 E2822004 add r2, r2, #4 ; Increment after 3391 00001FF4 3392 00001FF4 E2866004 stm_1 add r6, r6, #4 ; Move on one register 3393 00001FF8 E1560001 cmp r6, r1 ; Only matches for "^" cases 3394 00001FFC 0286601C addeq r6, r6, #sim_R13_user - sim_R13 ; Extra offset needed here 3395 00002000 ; (Offset is same for R8/FIQ) 3396 00002000 E1140004 tst r4, r4 ; 3397 00002004 1AFFFFF5 bne stm_loop ; Becomes EQ when last R4 bi t lost 3398 00002008 3399 00002008 E31A0902 tst r10, #LSM_PC_bit ; PC? 3400 0000200C 0A000010 beq lsm_out ; Almost always not 3401 00002010 3402 00002010 E28B0004 add r0, r11, #4 ; Synthesize PC+8 ARM Macro Assembler Page 100 3403 00002014 E28FE038 adr lr, lsm_out ; Get `return' address 3404 00002018 EAFFFCB5 b write_memory_w ; and go 3405 0000201C 3406 0000201C ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 3407 0000201C 3408 0000201C E1B040A4 ldm_loop movs r4, r4, lsr #1 ; Next bit in reg. list 3409 00002020 3A000002 bcc ldm_1 ; clear 3410 00002024 EBFFFC1B bl read_memory_w ; 3411 00002028 E2822004 add r2, r2, #4 ; Increment after 3412 0000202C E5861000 str r1, [r6] ; 3413 00002030 3414 00002030 E2866004 ldm_1 add r6, r6, #4 ; Move on one register 3415 00002034 E1560000 cmp r6, r0 ; Only matches for "^" cases 3416 00002038 0286601C addeq r6, r6, #sim_R13_user - sim_R13 ; Extra offset needed here 3417 0000203C ; (Offset is same for R8/FIQ) 3418 0000203C E1140004 tst r4, r4 ; 3419 00002040 1AFFFFF5 bne ldm_loop ; Becomes EQ when last R4 bi t lost 3420 00002044 3421 00002044 E31A0902 tst r10, #LSM_PC_bit ; PC? 3422 00002048 0A000001 beq lsm_out ; 3423 0000204C 3424 0000204C EBFFFC11 bl read_memory_w ; 3425 00002050 E1A0B001 mov r11, r1 ; Value into PC 3426 00002054 ; and fall into ... 3427 00002054 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 3428 00002054 3429 00002054 E31A0602 lsm_out tst r10, #Wbit ; See if register writeback used 3430 00002058 0A000006 beq lsm_out1 ; No writeback 3431 0000205C 3432 0000205C E31A0502 tst r10, #Ubit ; 3433 00002060 00450103 subeq r0, r5, r3, lsl #2 ; If decrement mode 3434 00002064 10850103 addne r0, r5, r3, lsl #2 ; If increment mode 3435 00002068 3436 00002068 E1A0282A mov r2, r10, lsr #16 ; Fetch Rn 3437 0000206C E202200F and r2, r2, #&F ; 3438 00002070 E352000F cmp r2, #15 ; Test for PC as base reg. 3439 00002074 17890102 strne r0, [r9, r2, lsl #2] ; Current register map 3440 00002078 ; not needed moveq r11, r0 ; or PC 3441 00002078 3442 00002078 E31A0501 lsm_out1 tst r10, #LSM_S_bit ; S bit set? 3443 0000207C 131A0601 tstne r10, #Ldbit ; if so is it a load? 3444 00002080 131A0902 tstne r10, #LSM_PC_bit ; if so is PC also set? 3445 00002084 049DF004 ldreq pc, [sp], #4 ; Return if not all of these ARM Macro Assembler Page 101 3446 00002088 3447 00002088 EAFFFEDB b spsr_copy_up ; else flip reg. bank (LDM PC^) 3448 0000208C 3449 0000208C ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 3450 0000208C 3451 0000208C E31A0601 lsm_hat tst r10, #Ldbit ; Jump here if S bit set 3452 00002090 131A0902 tstne r10, #LSM_PC_bit ; LDM {PC}^ ? 3453 00002094 1AFFFFCE bne lsm_1 ; Exception return case 3454 00002098 3455 00002098 E21C100F ands r1, r12, #Mode_bits ; Z if user mode 3456 0000209C 1351000F cmpne r1, #System_mode ; or if system mode 3457 000020A0 0AFFFFCB beq lsm_1 ; R0 unchanged if current mo de OK 3458 000020A4 3459 000020A4 E3510001 cmp r1, #FIQ_mode ; Where is the gap in reg. bank? 3460 000020A8 03A000C4 moveq r0, #sim_R8 - Mon_RAM_start ; R8 if in FIQ mode 3461 000020AC 13A000D8 movne r0, #sim_R13 - Mon_RAM_start ; R13 if not 3462 000020B0 EAFFFFC7 b lsm_1 ; 3463 000020B4 3464 000020B4 ;------------------------------------------------------- ----------------------- 3465 000020B4 3466 000020B4 E31A0401 branch tst r10, #Lbit ; 3467 000020B8 1589B038 strne r11, [r9, #sim_R14 - reg_block] 3468 000020BC ; Store link PC 3469 000020BC E1A0040A mov r0, r10, lsl #8 ; 3470 000020C0 E08B0340 add r0, r11, r0, asr #6 ; Does sign extension 3471 000020C4 E280B004 add r11, r0, #4 ; Correct for PC+8 3472 000020C8 E49DF004 ldr pc, [sp], #4 ; Return 3473 000020CC 3474 000020CC ;------------------------------------------------------- ----------------------- 3475 000020CC 3476 000020CC E31A0401 sys tst r10, #&01000000 ; Possibly a copro op. 3477 000020D0 0A000001 beq sys_copro ; 3478 000020D4 ; SWI 3479 000020D4 E28FA054 adr r10, SWI_data ; R10 safe - usually IR 3480 000020D8 EA000006 b exception_entry ; 3481 000020DC 3482 000020DC ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 3483 000020DC 3484 000020DC lsc ; For now drop into undefine d 3485 000020DC sys_copro ; For now drop into undefine d 3486 000020DC 3487 000020DC E28FA052 undef adr r10, undef_data ; R10 safe - usually IR 3488 000020E0 EA000004 b exception_entry ; ARM Macro Assembler Page 102 3489 000020E4 3490 000020E4 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 3491 000020E4 3492 000020E4 E52DE004 IRQ_entry str lr, [sp, #-4]! ; 3493 000020E8 E28FA04C adr r10, IRQ_data ; R10 safe - usually IR 3494 000020EC EA000001 b exception_entry ; 3495 000020F0 3496 000020F0 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 3497 000020F0 3498 000020F0 E52DE004 FIQ_entry str lr, [sp, #-4]! ; 3499 000020F4 E28FA046 adr r10, FIQ_data ; R10 safe - usually IR 3500 000020F8 3501 000020F8 E5DA1000 exception_entry ldrb r1, [r10] ; Get SPSR offset 3502 000020FC E789C001 str r12, [r9, r1] ; Save current CPSR 3503 00002100 E5DA1001 ldrb r1, [r10, #1] ; Get new mode code 3504 00002104 E20C000F and r0, r12, #&F ; Current mode 3505 00002108 EB00000E bl mode_reg_swap ; Trashes registers :-( no t R10 3506 0000210C E5DA1002 ldrb r1, [r10, #2] ; Get mode mask 3507 00002110 E1CCC001 bic r12, r12, r1 ; Lose most/all of status 3508 00002114 E5DA1003 ldrb r1, [r10, #3] ; Get new mode bits 3509 00002118 E18CC001 orr r12, r12, r1 ; 3510 0000211C E5DA1004 ldrb r1, [r10, #4] ; Get LR offset 3511 00002120 E08BB001 add r11, r11, r1 ; Adjust PC before saving 3512 00002124 E589B038 str r11, [r9, #sim_R14 - reg_block] 3513 00002128 ; Save link (new mode) 3514 00002128 E5DAB005 ldrb r11, [r10, #5] ; Set PC for exception 3515 0000212C E49DF004 ldr pc, [sp], #4 ; Return 3516 00002130 3517 00002130 3518 00002130 94 SWI_data DCB sim_SPSR_svc - reg_block ; SPSR offset 3519 00002131 03 DCB Supervisor_mode ; 3520 00002132 BF DCB &BF ; Bits cleared in mode byte 3521 00002133 93 DCB I_bit :OR: mode32 :OR: Supervisor_mode 3522 00002134 00 DCB 0 ; LR offset 3523 00002135 08 DCB &08 ; `Vector' address 3524 00002136 3525 00002136 9C undef_data DCB sim_SPSR_undef-reg_block ; SPSR offset 3526 00002137 0B DCB Undefined_mode ; 3527 00002138 BF DCB &BF ; Bits cleared in mode byte 3528 00002139 9B DCB I_bit :OR: mode32 :OR: Undefined_mode 3529 0000213A 00 DCB 0 ; LR offset 3530 0000213B 04 DCB &04 ; `Vector' address 3531 0000213C 3532 0000213C A0 IRQ_data DCB sim_SPSR_irq - reg_block ; SPSR offset 3533 0000213D 02 DCB IRQ_mode ; 3534 0000213E BF DCB &BF ; Bits cleared in mode byte 3535 0000213F 92 DCB I_bit :OR: mode32 :OR: IRQ_mode ARM Macro Assembler Page 103 3536 00002140 04 DCB 4 ; LR offset 3537 00002141 18 DCB &18 ; `Vector' address 3538 00002142 3539 00002142 A4 FIQ_data DCB sim_SPSR_fiq - reg_block ; SPSR offset 3540 00002143 01 DCB FIQ_mode ; 3541 00002144 FF DCB &FF ; Bits cleared in mode byte 3542 00002145 D1 DCB I_bit :OR: F_bit :OR: mode32 :OR: FIQ_mo de 3543 00002146 04 DCB 4 ; LR offset 3544 00002147 1C DCB &1C ; `Vector' address 3545 00002148 3546 00002148 ALIGN 3547 00002148 ;------------------------------------------------------- ----------------------- 3548 00002148 ; Swap register map from mode R0 to mode R1 3549 00002148 ; Needs r9 => register bank 3550 00002148 ; Corrupts r0-r6 3551 00002148 3552 00002148 E28F2068 mode_reg_swap adr r2, reg_start_tab ; Pointer to register position 3553 0000214C E3500001 cmp r0, #FIQ_mode ; 3554 00002150 13510001 cmpne r1, #FIQ_mode ; 3555 00002154 1A00000D bne mode_reg_swap_no_FIQ ; 3556 00002158 3557 00002158 E92D0084 stmfd sp!, {r2, r7} ; Need to move 5 more regi sters 3558 0000215C E3500001 cmp r0, #FIQ_mode ; From FIQ? 3559 00002160 02892078 addeq r2, r9, #sim_R8_FIQ - reg_block ; Yes! 3560 00002164 1289203C addne r2, r9, #sim_R8_user - reg_block ; No, user 3561 00002168 E2899020 add r9, r9, #sim_R8 - reg_block ; Start with R8 3562 0000216C E89900F8 ldmia r9, {r3-r7} ; Out with the old 3563 00002170 E88200F8 stmia r2, {r3-r7} ; 3564 00002174 3565 00002174 E3510001 cmp r1, #FIQ_mode ; To FIQ? 3566 00002178 02892058 addeq r2, r9, #sim_R8_FIQ - sim_R8 3567 0000217C ; Yes! (R9 already offset to =>R8) 3568 0000217C 1289201C addne r2, r9, #sim_R8_user - sim_R8 ; No, user 3569 00002180 E89200F8 ldmia r2, {r3-r7} ; In with the new 3570 00002184 E88900F8 stmia r9, {r3-r7} ; 3571 00002188 3572 00002188 E2499020 sub r9, r9, #sim_R8 - reg_block ; Put R9 correct again 3573 0000218C E8BD0084 ldmfd sp!, {r2, r7} ; 3574 00002190 3575 00002190 mode_reg_swap_no_FIQ 3576 00002190 E7D20000 ldrb r0, [r2, r0] ; Old reg. offset 3577 00002194 E7D21001 ldrb r1, [r2, r1] ; New reg. offset 3578 00002198 E0890100 add r0, r9, r0, lsl #2 ; Old reg. base 3579 0000219C E0891101 add r1, r9, r1, lsl #2 ; New reg. base 3580 000021A0 E2892034 add r2, r9, #sim_R13 - reg_block ; Start at R13 3581 000021A4 E8920018 ldmia r2, {r3, r4} ; Out with the old 3582 000021A8 E8800018 stmia r0, {r3, r4} ; ARM Macro Assembler Page 104 3583 000021AC E8910018 ldmia r1, {r3, r4} ; In with the new 3584 000021B0 E8820018 stmia r2, {r3, r4} ; 3585 000021B4 E1A0F00E mov pc, lr ; 3586 000021B8 3587 000021B8 ; R13 offsets 3588 000021B8 14 reg_start_tab DCB (sim_R13_user - reg_block)/4 ; User 3589 000021B9 23 DCB (sim_R13_FIQ - reg_block)/4 ; FIQ 3590 000021BA 1C DCB (sim_R13_IRQ - reg_block)/4 ; IRQ 3591 000021BB 16 DCB (sim_R13_svc - reg_block)/4 ; Supervisor 3592 000021BC 00 DCB 0 ; 3593 000021BD 00 DCB 0 ; 3594 000021BE 00 DCB 0 ; 3595 000021BF 18 DCB (sim_R13_abt - reg_block)/4 ; Abort 3596 000021C0 00 DCB 0 ; 3597 000021C1 00 DCB 0 ; 3598 000021C2 00 DCB 0 ; 3599 000021C3 1A DCB (sim_R13_undef - reg_block)/4 ; Undefined 3600 000021C4 00 DCB 0 ; 3601 000021C5 00 DCB 0 ; 3602 000021C6 00 DCB 0 ; 3603 000021C7 14 DCB (sim_R13_user - reg_block)/4 ; System 3604 000021C8 3605 000021C8 ALIGN 3606 000021C8 3607 000021C8 ;------------------------------------------------------- ----------------------- 3608 000021C8 ; Returns value in R1, CF = shifter_carry_out 3609 000021C8 3610 000021C8 E20A100F shifted_Rm and r1, r10, #&F ; 3611 000021CC E351000F cmp r1, #&F ; Test for PC 3612 000021D0 17991101 ldrne r1, [r9, r1, lsl #2] ; Current register map 3613 000021D4 028B1004 addeq r1, r11, #4 ; or PC 3614 000021D8 3615 000021D8 E31A0EFF tst r10, #&00000FF0 ; R1 already loaded 3616 000021DC 1A000001 bne shifted_Rm1 ; 3617 000021E0 ; Fall through if unshifted 3618 000021E0 3619 000021E0 E11C018C tst r12, r12, lsl #3 ; Set CF to carry 3620 000021E4 E1A0F00E mov pc, lr ; and return in most freque nt case 3621 000021E8 3622 000021E8 E20A0060 shifted_Rm1 and r0, r10, #&60 ; R0 := shift type 3623 000021EC E31A0010 tst r10, #&00000010 ; Register based shift? 3624 000021F0 1A000007 bne shifted_Rm_reg ; 3625 000021F4 E1A023AA mov r2, r10, lsr #7 ; 3626 000021F8 E212201F ands r2, r2, #&1F ; R2 := shift amount 3627 000021FC 03822020 orreq r2, r2, #&20 ; 0=>32 (LSL already gone) 3628 00002200 03500060 cmpeq r0, #&60 ; RRX? 3629 00002204 1A000007 bne do_shift ; 3630 00002208 3631 00002208 E11C018C tst r12, r12, lsl #3 ; Set CF to carry ARM Macro Assembler Page 105 3632 0000220C E1B01061 movs r1, r1, rrx ; 3633 00002210 E1A0F00E mov pc, lr ; 3634 00002214 3635 00002214 3636 00002214 E20A2C0F shifted_Rm_reg and r2, r10, #&00000F00 ; Rs field 3637 00002218 E3520C0F cmp r2, #&00000F00 ; Test for PC 3638 0000221C 17992322 ldrne r2, [r9, r2, lsr #6] ; Current register map 3639 00002220 028B2004 addeq r2, r11, #4 ; or PC 3640 00002224 E20220FF and r2, r2, #&FF ; Bottom byte only 3641 00002228 3642 00002228 E11C018C do_shift tst r12, r12, lsl #3 ; Set CF to carry 3643 0000222C E08FF120 add pc, pc, r0, lsr #2 ; Index in 2 word steps 3644 00002230 E1A00000 nop ; Can use this word for data @@@ 3645 00002234 ; PC based on next instruction 3646 00002234 E1B01211 shift_lsl movs r1, r1, lsl r2 ; LSL 3647 00002238 E1A0F00E mov pc, lr ; CF = shifter_carry_out 3648 0000223C 3649 0000223C E1B01231 shift_lsr movs r1, r1, lsr r2 ; LSR 3650 00002240 E1A0F00E mov pc, lr ; CF = shifter_carry_out 3651 00002244 3652 00002244 E1B01251 shift_asr movs r1, r1, asr r2 ; ASR 3653 00002248 E1A0F00E mov pc, lr ; CF = shifter_carry_out 3654 0000224C 3655 0000224C E1B01271 shift_ror movs r1, r1, ror r2 ; ROR 3656 00002250 E1A0F00E mov pc, lr ; CF = shifter_carry_out 3657 00002254 3658 00002254 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 3659 00002254 3660 00002254 E1A003AA immediate mov r0, r10, lsr #7 ; 3661 00002258 E200001E and r0, r0, #&1E ; Rotate amount 3662 0000225C E20A10FF and r1, r10, #&FF ; Immediate byte 3663 00002260 E11C018C tst r12, r12, lsl #3 ; Set CF to carry 3664 00002264 E1B01071 movs r1, r1, ror r0 ; Carry set if required 3665 00002268 E1A0F00E mov pc, lr ; 3666 0000226C ; CPSR carry flag is shifter_carry_out 3667 0000226C 3668 0000226C E200000F read_reg and r0, r0, #&F ; 3669 00002270 E350000F cmp r0, #&F ; Test for PC 3670 00002274 17990100 ldrne r0, [r9, r0, lsl #2] ARM Macro Assembler Page 106 ; Current register map 3671 00002278 028B0004 addeq r0, r11, #4 ; or PC 3672 0000227C E1A0F00E mov pc, lr ; 3673 00002280 3674 00002280 E20A0A0F write_reg and r0, r10, #&0000F000 ; Rd 3675 00002284 E3500A0F cmp r0, #&0000F000 ; Test for PC 3676 00002288 17891520 strne r1, [r9, r0, lsr #10] ; Current register map 3677 0000228C 01A0B001 moveq r11, r1 ; or PC 3678 00002290 E1A0F00E mov pc, lr ; 3679 00002294 3680 00002294 ;------------------------------------------------------- ----------------------- 3681 00002294 ; Check for breakpoint - address R2, data R1 3682 00002294 ; Corrupts R0 (or uses it for breakpoint number) 3683 00002294 ; Returns carry set if breakpoint NOT found 3684 00002294 ; Not suitable for watchpoints yet @@@ 3685 00002294 3686 00002294 E92D4038 breakpoint_check stmfd sp!, {r3-r5, lr} ; 3687 00002298 3688 00002298 E3A03F5A mov r3, #breakpoint_table - Mon_RAM_start 3689 0000229C E3A00000 mov r0, #0 3690 000022A0 3691 000022A0 E5D3E000 brkpt_rpt ldrb r14, [r3, #BP_active - breakpoint_table] 3692 000022A4 ; Look at flag 3693 000022A4 E35E0003 cmp r14, #3 ; This one active? 3694 000022A8 1A000030 bne brkpt_next ; No, move along 3695 000022AC 3696 000022AC E1D350B2 ldrh r5, [r3, #BP_type] ; Cheat, fetching halfword! 3697 000022B0 E3150B01 tst r5, #&0400 ; 32-bit allowed? 3698 000022B4 0A00002D beq brkpt_next ; No, move along 3699 000022B8 E3150020 tst r5, #&0020 ; Read allowed? 3700 000022BC 0A00002B beq brkpt_next ; No, move along 3701 000022C0 3702 000022C0 ; Mode is in R12 EXCEPT for watchpoints during LSM^ @@@ 3703 000022C0 E31C000F tst r12, #&F ; Get fetch mode 3704 000022C4 03A04080 moveq r4, #&80 ; In user mode 3705 000022C8 13A04040 movne r4, #&40 ; In kernel mode 3706 000022CC E1150004 tst r5, r4 ; Check mode is legal 3707 000022D0 0A000026 beq brkpt_next ; Tested bit clear 3708 000022D4 3709 000022D4 E593E004 ldr r14, [r3, #BP_addr_A] ; Start address comparison 3710 000022D8 E215400C ands r4, r5, #&000C ; Address comparison type 3711 000022DC 0A000023 beq brkpt_next ; 00 not defined 3712 000022E0 E3540008 cmp r4, #&0008 ; 3713 000022E4 0A000005 beq brkpt_1 ; 10 is a <= x <= b 3714 000022E8 3A000020 blo brkpt_next ; 01 not defined 3715 000022EC 3716 000022EC E022400E eor r4, r2, r14 ; Set unequal bits 3717 000022F0 E593E008 ldr r14, [r3, #BP_addr_B] ; ARM Macro Assembler Page 107 3718 000022F4 E114000E tst r4, r14 ; Mask off don't cares 3719 000022F8 1A00001C bne brkpt_next ; Some bits still don't matc h 3720 000022FC EA000004 b brkpt_2 ; Now try data ... 3721 00002300 3722 00002300 E152000E brkpt_1 cmp r2, r14 ; 3723 00002304 3A000019 blo brkpt_next ; 3724 00002308 E593E008 ldr r14, [r3, #BP_addr_B] ; 3725 0000230C E152000E cmp r2, r14 ; 3726 00002310 8A000016 bhi brkpt_next ; 3727 00002314 3728 00002314 E593E00C brkpt_2 ldr r14, [r3, #BP_data_A] ; Start data comparison 3729 00002318 E2154003 ands r4, r5, #&0003 ; Data comparison type 3730 0000231C 0A000013 beq brkpt_next ; 00 not defined 3731 00002320 E3540002 cmp r4, #&0002 ; 3732 00002324 0A000005 beq brkpt_3 ; 10 is a <= x <= b 3733 00002328 3A000010 blo brkpt_next ; 01 not defined 3734 0000232C 3735 0000232C E021400E eor r4, r1, r14 ; Set unequal bits 3736 00002330 E593E014 ldr r14, [r3, #BP_data_B] ; 3737 00002334 E114000E tst r4, r14 ; Mask off don't cares 3738 00002338 1A00000C bne brkpt_next ; Some bits still don't matc h 3739 0000233C EA000005 b brkpt_4 ; Found one! 3740 00002340 3741 00002340 E593E00C brkpt_3 ldr r14, [r3, #BP_data_A] ; Data comparison 3742 00002344 E151000E cmp r1, r14 ; 3743 00002348 3A000008 blo brkpt_next ; 3744 0000234C E593E014 ldr r14, [r3, #BP_data_B] ; 3745 00002350 E151000E cmp r1, r14 ; 3746 00002354 8A000005 bhi brkpt_next ; 3747 00002358 3748 00002358 3749 00002358 E5D7400C brkpt_4 ldrb r4, [r7, #arm_state - shared_variables] 3750 0000235C E5C7400D strb r4, [r7, #arm_state_old - shared_variabl es] 3751 00002360 E3A04042 mov r4, #State_stop_bkpt ; Stop (Breakpoint number in R0) 3752 00002364 E5C7400C strb r4, [r7, #arm_state - shared_variables] 3753 00002368 ; Signal to processor 3754 00002368 3755 00002368 E3B03AFF movs r3, #&000FF000 ; Clear carry flag 3756 0000236C EA000003 b brkpt_out ; to indicate breakpoint fo und 3757 00002370 3758 00002370 3759 00002370 E283301C brkpt_next add r3, r3, #brk_pt_rcd_length 3760 00002374 E2800001 add r0, r0, #1 ; Count up until ... 3761 00002378 E3500008 cmp r0, #breakpoint_max ; 3762 0000237C 3AFFFFC7 blo brkpt_rpt ; (i.e. carry clear) 3763 00002380 3764 00002380 E8BD8038 ARM Macro Assembler Page 108 brkpt_out ldmfd sp!, {r3-r5, pc} ; Carry set if okay 3765 00002384 3766 00002384 ;------------------------------------------------------- ----------------------- 3767 00002384 3768 00002384 RAM_image_end ; New label 3769 00002384 3770 00002384 END