;------------------------------------------------------------------------------ ; Headers and definitions for AT91 basic set up. ; Last modified 10/1/03 ; General ARM headers SP RN R13 ; Register synonyms LR RN R14 PC RN R15 H0 RN R8 ; Thumb register synonyms H1 RN R9 H2 RN R10 H3 RN R11 H4 RN R12 H5 RN R13 H6 RN R14 H7 RN R15 I_bit EQU &00000080 ; Interrupt disable bit in status word F_bit EQU &00000040 ; FIQ disable bit in status word T_bit EQU &00000020 ; Thumb bit mask in status word TRUE EQU -1 FALSE EQU 0 Mode_bits EQU &F ; Bits considered as operating mode User_mode EQU &0 FIQ_mode EQU &1 IRQ_mode EQU &2 Supervisor_mode EQU &3 Abort_mode EQU &7 Undefined_mode EQU &B System_mode EQU &F mode32 EQU &10 ;------------------------------------------------------------------------------ cEOT EQU 4 ; Basic ASCII characters cLF EQU 10 cFF EQU 12 cCR EQU 13 ttr EQU 0 ; String terminator byte3 EQU &FF000000 ; Byte masks byte2 EQU &00FF0000 byte1 EQU &0000FF00 byte0 EQU &000000FF ;------------------------------------------------------------------------------ ; Specific header for AT91 board FASTRAM_base EQU &00000000 ; Prescribed - run time address RAM_chip_size EQU &00080000 ; 512 Kbytes ROM_base EQU &08000000 ; These are chosen by the user RAM_base EQU &10000000 VIRTEX_base EQU &20000000 ETHERNET_base EQU &30000000 SPARTAN_base EQU &40000000 ; Flags passed to application LCD_present_flag EQU &00000001 ; If LCD detected Power_up_flag EQU &00000100 ; If power-up reset Watchdogged_flag EQU &00000200 ; If watchdog reset ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Serial_number_addr EQU &3FFC ; boot_table_address EQU &4000 ; 16Kbytes up to clear bottom block ; Boot programme MUST be shorter boot_table_shifts EQU 8 ; Log of boot table length (&100) boot_table_entry_length EQU 1 :SHL: boot_table_shifts ; Can't define this the other way :-( ; Boot block offsets (don't really belong here) Btab_flags EQU &04 Btab_RAM_start EQU &08 Btab_RAM_length EQU &0C Btab_ROM_start EQU &10 Btab_ROM_length EQU &14 Btab_exec_offset EQU &18 Btab_exec_CPSR EQU &1C Btab_spartan_data EQU &20 Btab_spartan_length EQU &24 Btab_virtex_data EQU &28 Btab_virtex_length EQU &2C Btab_LCD_message EQU &30 ; Boot flag definitions BtFlg_LCD_message EQU &00000001 BtFlg_LCD_light EQU &00000002 BtFlg_LED_on EQU &00000004 BtFlg_RAM_boot EQU &00000008 ; TBC BtFlg_ROM_check EQU &00000010 BtFlg_RAM_clr_int EQU &00000100 BtFlg_RAM_clr_ext EQU &00000200 ; FPGA block offsets (don't really belong here either) FPGA_offset EQU 4 FPGA_length EQU 8 ; Default stack sizes (user gets remainder) Supervisor_stack EQU &200 FIQ_stack EQU &80 IRQ_stack EQU &80 Abort_stack EQU &80 Undefined_stack EQU &80 ;------------------------------------------------------------------------------ ; AT91 on-board register definitions DEV_TERMINATE EQU -1 ; Not a peripheral address ; used to terminate set-up tables ; External bus interface register addresses EBI_base EQU &FFE00000 EBI_CSR0 EQU &00 EBI_CSR1 EQU &04 EBI_CSR2 EQU &08 EBI_CSR3 EQU &0C EBI_CSR4 EQU &10 EBI_CSR5 EQU &14 EBI_CSR6 EQU &18 EBI_CSR7 EQU &1C EBI_RCR EQU &20 EBI_MCR EQU &24 ; EBI CSR bit fields CSEN EQU &00002000 ; Chip select enable BAT EQU &00001000 ; Byte access type (byte select) TDF1 EQU &00000200 ; One data float cycle TDF2 EQU &00000400 ; Two data float cycles TDF3 EQU &00000600 ; Three data float cycles TDF4 EQU &00000800 ; Four data float cycles TDF5 EQU &00000A00 ; Five data float cycles TDF6 EQU &00000C00 ; Six data float cycles TDF7 EQU &00000E00 ; Seven data float cycles Pg1M EQU &00000000 ; 1 Mbyte pages Pg4M EQU &00000080 ; 4 Mbyte pages Pg16M EQU &00000100 ; 16 Mbyte pages Pg64M EQU &00000180 ; 64 Mbyte pages NWS1 EQU &00000020 ; 1 wait state (WSE included) NWS2 EQU &00000024 ; 2 wait states NWS3 EQU &00000028 ; 3 wait states NWS4 EQU &0000002C ; 4 wait states NWS5 EQU &00000030 ; 5 wait states NWS6 EQU &00000034 ; 6 wait states NWS7 EQU &00000038 ; 7 wait states NWS8 EQU &0000003C ; 8 wait states DBW8 EQU &00000002 ; 8-bit bus DBW16 EQU &00000001 ; 16-bit bus ; "Special function" register addresses SF_base EQU &FFF00000 SF_CIDR EQU &00 SF_EXID EQU &04 SF_RSR EQU &08 SF_MMR EQU &0C SF_PMR EQU &18 ; PIO register addresses PIO_base EQU &FFFF0000 PIO_PER EQU &00 PIO_PDR EQU &04 PIO_PSR EQU &08 PIO_OER EQU &10 PIO_ODR EQU &14 PIO_OSR EQU &18 PIO_IFER EQU &20 PIO_IFDR EQU &24 PIO_IFSR EQU &28 PIO_SODR EQU &30 PIO_CODR EQU &34 PIO_ODSR EQU &38 PIO_PDSR EQU &3C PIO_IER EQU &40 PIO_IDR EQU &44 PIO_IMR EQU &48 PIO_ISR EQU &4C ; Power saving register addresses PS_base EQU &FFFF4000 PS_CR EQU &00 PS_PCER EQU &04 PS_PCDR EQU &08 PS_PCSR EQU &0C ; Watchdog register addresses WD_base EQU &FFFF8000 WD_OMR EQU &00 WD_CMR EQU &04 WD_CR EQU &08 WD_SR EQU &0C ; USART[0:1] register addresses US0_base EQU &FFFD0000 ; Serial port 0 US1_base EQU &FFFCC000 ; Serial port 1 US_CR EQU &00 US_MR EQU &04 US_IER EQU &08 US_IDR EQU &0C US_IMR EQU &10 US_CSR EQU &14 US_RHR EQU &18 US_THR EQU &1C US_BRGR EQU &20 US_RTOR EQU &24 US_TTGR EQU &28 US_RPR EQU &30 US_RCR EQU &34 US_TPR EQU &38 US_TCR EQU &3C ; USART bit definitions RxRdy EQU &001 ; Channel Status Register bits TxRdy EQU &002 RxBrk EQU &004 EndRx EQU &008 EndTx EQU &010 OvrE EQU &020 FramE EQU &040 ParE EQU &080 Timeout EQU &100 TxEmpty EQU &200 ; Timer/Counter register addresses TC_base EQU &FFFE0000 TC_CHL0 EQU &00 ; Base offset for TC0 TC_CHL1 EQU &40 ; Base offset for TC1 TC_CHL2 EQU &80 ; Base offset for TC2 TC_BCR EQU &C0 ; Block control register TC_BMR EQU &C4 ; Block mode register ; Register offsets within for TC TC_CCR EQU &00 TC_CMR EQU &04 TC_CVR EQU &10 TC_RA EQU &14 TC_RB EQU &18 TC_RC EQU &1C TC_SR EQU &20 TC_IER EQU &24 TC_IDR EQU &28 TC_IMR EQU &2C ; Interrupt controller register addresses AIC_base EQU &FFFFF000 AIC_SMR0 EQU &00 ; Source mode/priority - FIQ AIC_SMR1 EQU &04 ; Source mode/priority - Software AIC_SMR2 EQU &08 ; Source mode/priority - USART #0 AIC_SMR3 EQU &0C ; Source mode/priority - USART #1 AIC_SMR4 EQU &10 ; Source mode/priority - Timer #0 AIC_SMR5 EQU &14 ; Source mode/priority - Timer #1 AIC_SMR6 EQU &18 ; Source mode/priority - Timer #2 AIC_SMR7 EQU &1C ; Source mode/priority - Watchdog AIC_SMR8 EQU &20 ; Source mode/priority - PIO AIC_SMR16 EQU &40 ; Source mode/priority - IRQ #0 (Spartan) AIC_SMR17 EQU &44 ; Source mode/priority - IRQ #1 (Virtex) AIC_SMR18 EQU &48 ; Source mode/priority - IRQ #2 (Ethernet) AIC_SVR0 EQU &80 ; Source vector - FIQ AIC_SVR1 EQU &84 ; Source vector - Software AIC_SVR2 EQU &88 ; Source vector - USART #0 AIC_SVR3 EQU &8C ; Source vector - USART #1 AIC_SVR4 EQU &90 ; Source vector - Timer #0 AIC_SVR5 EQU &94 ; Source vector - Timer #1 AIC_SVR6 EQU &98 ; Source vector - Timer #2 AIC_SVR7 EQU &9C ; Source vector - Watchdog AIC_SVR8 EQU &A0 ; Source vector - PIO AIC_SVR16 EQU &C0 ; Source vector - IRQ #0 (Spartan) AIC_SVR17 EQU &C4 ; Source vector - IRQ #1 (Virtex) AIC_SVR18 EQU &C8 ; Source vector - IRQ #2 (Ethernet) AIC_IVR EQU &100 ; Vector register (IRQ) AIC_FVR EQU &104 ; Vector register (FIQ) AIC_ISR EQU &108 ; Interrupt status AIC_IPR EQU &10C ; (Potential) interrupts pending AIC_IMR EQU &110 ; Interrupt mask AIC_CISR EQU &114 ; Core IRQ/FIQ status AIC_IECR EQU &120 ; Interrupt enable AIC_IDCR EQU &124 ; Interrupt disable AIC_ICCR EQU &128 ; Interrupt clear AIC_ISCR EQU &12C ; Interrupt set AIC_EOICR EQU &130 ; Signal end of interrupt AIC_SPU EQU &134 ; Spurious interrupt vector ;------------------------------------------------------------------------------ ; `Magic' numbers used to derive baud rate divider from clock speed baud115k2 EQU &0001D7DC ; 0.1152 * &10000 * 16 baud38k4 EQU &00009D49 ; 0.0384 * &10000 * 16 baud19k2 EQU &00004EA5 ; 0.0192 * &10000 * 16 baud9600 EQU &00002752 ; 0.0096 * &10000 * 16 ;------------------------------------------------------------------------------ ; Local PIO bit definitions for AT91 board AT91_Spartan_IRQ EQU &00000200 ; AT91_Virtex_IRQ EQU &00000400 ; AT91_Ether_IRQ EQU &00000800 ; AT91_FIQ EQU &00001000 ; Open drain (Also HDC signal) AT91_Spartan_prog EQU &00010000 ; Active low AT91_Virtex_prog EQU &00020000 ; Active low AT91_Spartan_init EQU &00040000 ; Active low input AT91_Virtex_init EQU &00080000 ; Active low input AT91_Spartan_CS1 EQU &00800000 ; Also LCD_RS AT91_Spartan_HDC EQU &00001000 ; Also FIQ signal AT91_FPGA_baud EQU &00002000 ; Also DOUT - ; driven low by Spartan at configuration time AT91_LCD_light EQU &00100000 ; AT91_LCD_RS EQU &00800000 ; Also Spartan CS1 AT91_LCD_En EQU &01000000 ; AT91_LCD_RW EQU &02000000 ; AT91_LED_En EQU &40000000 ; AT91_LCD_busy EQU &00000080 ; MSB of data bus ;------------------------------------------------------------------------------ prog_SA0_data EQU &0 ; XPIO register offsets prog_SA0_ctrl EQU &1 prog_SA1_data EQU &2 prog_SA1_ctrl EQU &3 prog_SB0_data EQU &4 prog_SB0_ctrl EQU &5 prog_SB1_data EQU &6 prog_SB1_ctrl EQU &7 prog_VS0_data EQU &8 prog_VS0_ctrl EQU &9 prog_VS1_data EQU &A prog_VS1_ctrl EQU &B ;------------------------------------------------------------------------------ END