ARM Macro Assembler Page 1 1 00000000 ;------------------------------------------------------- ----------------------- 2 00000000 ; Manchester University ARM/Xilinx board software 3 00000000 ; Off-board Flash ROM programming code 4 00000000 ; 5 00000000 ; J. Garside November 2001 6 00000000 7 00000000 8 00000000 00000000 Maker EQU 0 9 00000000 00000000 Version EQU 0 10 00000000 00000015 day EQU 21 11 00000000 0000000B month EQU 11 12 00000000 00000001 year EQU 01 13 00000000 14 00000000 15 00000000 GET header.s ; Register definitions etc. 1 00000000 ;------------------------------------------------------- ----------------------- 2 00000000 ; Headers and definitions for AT91 basic set up. 3 00000000 ; Last modified 10/1/03 4 00000000 5 00000000 ; General ARM headers 6 00000000 7 00000000 D SP RN R13 ; Register synonyms 8 00000000 E LR RN R14 9 00000000 F PC RN R15 10 00000000 11 00000000 8 H0 RN R8 ; Thumb register synonyms 12 00000000 9 H1 RN R9 13 00000000 A H2 RN R10 14 00000000 B H3 RN R11 15 00000000 C H4 RN R12 16 00000000 D H5 RN R13 17 00000000 E H6 RN R14 18 00000000 F H7 RN R15 19 00000000 20 00000000 00000080 I_bit EQU &00000080 ; Interrupt disable bit in s tatus word 21 00000000 00000040 F_bit EQU &00000040 ; FIQ disable bit in status word 22 00000000 00000020 ARM Macro Assembler Page 2 T_bit EQU &00000020 ; Thumb bit mask in status w ord 23 00000000 24 00000000 FFFFFFFF TRUE EQU -1 25 00000000 00000000 FALSE EQU 0 26 00000000 27 00000000 0000000F Mode_bits EQU &F ; Bits considered as operati ng mode 28 00000000 00000000 User_mode EQU &0 29 00000000 00000001 FIQ_mode EQU &1 30 00000000 00000002 IRQ_mode EQU &2 31 00000000 00000003 Supervisor_mode EQU &3 32 00000000 00000007 Abort_mode EQU &7 33 00000000 0000000B Undefined_mode EQU &B 34 00000000 0000000F System_mode EQU &F 35 00000000 36 00000000 00000010 mode32 EQU &10 37 00000000 38 00000000 ;------------------------------------------------------- ----------------------- 39 00000000 40 00000000 00000004 cEOT EQU 4 ; Basic ASCII characters 41 00000000 0000000A cLF EQU 10 42 00000000 0000000C cFF EQU 12 43 00000000 0000000D cCR EQU 13 44 00000000 45 00000000 00000000 ttr EQU 0 ; String terminator 46 00000000 47 00000000 FF000000 byte3 EQU &FF000000 ; Byte masks 48 00000000 00FF0000 byte2 EQU &00FF0000 49 00000000 0000FF00 byte1 EQU &0000FF00 50 00000000 000000FF ARM Macro Assembler Page 3 byte0 EQU &000000FF 51 00000000 52 00000000 ;------------------------------------------------------- ----------------------- 53 00000000 ; Specific header for AT91 board 54 00000000 55 00000000 00000000 FASTRAM_base EQU &00000000 ; Prescribed - run time addr ess 56 00000000 57 00000000 00080000 RAM_chip_size EQU &00080000 ; 512 Kbytes 58 00000000 59 00000000 08000000 ROM_base EQU &08000000 ; These are chosen by the us er 60 00000000 10000000 RAM_base EQU &10000000 61 00000000 20000000 VIRTEX_base EQU &20000000 62 00000000 30000000 ETHERNET_base EQU &30000000 63 00000000 40000000 SPARTAN_base EQU &40000000 64 00000000 65 00000000 66 00000000 ; Flags passed to application 67 00000000 00000001 LCD_present_flag EQU &00000001 ; If LCD detected 68 00000000 00000100 Power_up_flag EQU &00000100 ; If power-up reset 69 00000000 00000200 Watchdogged_flag EQU &00000200 ; If watchdog reset 70 00000000 71 00000000 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 72 00000000 73 00000000 00003FFC Serial_number_addr EQU &3FFC ; 74 00000000 75 00000000 00004000 boot_table_address EQU &4000 ; 16Kbytes up to clear botto m block 76 00000000 ; Boot programme MUST be shorter 77 00000000 00000008 boot_table_shifts EQU 8 ; Log of boot table length ( ARM Macro Assembler Page 4 &100) 78 00000000 00000100 boot_table_entry_length EQU 1 :SHL: boot_table_shifts 79 00000000 ; Can't define this the other way :-( 80 00000000 81 00000000 ; Boot block offsets (don't really belong here) 82 00000000 83 00000000 00000004 Btab_flags EQU &04 84 00000000 00000008 Btab_RAM_start EQU &08 85 00000000 0000000C Btab_RAM_length EQU &0C 86 00000000 00000010 Btab_ROM_start EQU &10 87 00000000 00000014 Btab_ROM_length EQU &14 88 00000000 00000018 Btab_exec_offset EQU &18 89 00000000 0000001C Btab_exec_CPSR EQU &1C 90 00000000 00000020 Btab_spartan_data EQU &20 91 00000000 00000024 Btab_spartan_length EQU &24 92 00000000 00000028 Btab_virtex_data EQU &28 93 00000000 0000002C Btab_virtex_length EQU &2C 94 00000000 00000030 Btab_LCD_message EQU &30 95 00000000 96 00000000 ; Boot flag definitions 97 00000000 00000001 BtFlg_LCD_message EQU &00000001 98 00000000 00000002 BtFlg_LCD_light EQU &00000002 99 00000000 00000004 BtFlg_LED_on EQU &00000004 100 00000000 00000008 BtFlg_RAM_boot EQU &00000008 ; TBC 101 00000000 00000010 ARM Macro Assembler Page 5 BtFlg_ROM_check EQU &00000010 102 00000000 00000100 BtFlg_RAM_clr_int EQU &00000100 103 00000000 00000200 BtFlg_RAM_clr_ext EQU &00000200 104 00000000 105 00000000 ; FPGA block offsets (don't really belong here either) 106 00000000 107 00000000 00000004 FPGA_offset EQU 4 108 00000000 00000008 FPGA_length EQU 8 109 00000000 110 00000000 111 00000000 ; Default stack sizes (user gets remainder) 112 00000000 113 00000000 00000200 Supervisor_stack EQU &200 114 00000000 00000080 FIQ_stack EQU &80 115 00000000 00000080 IRQ_stack EQU &80 116 00000000 00000080 Abort_stack EQU &80 117 00000000 00000080 Undefined_stack EQU &80 118 00000000 119 00000000 ;------------------------------------------------------- ----------------------- 120 00000000 ; AT91 on-board register definitions 121 00000000 122 00000000 FFFFFFFF DEV_TERMINATE EQU -1 ; Not a peripheral address 123 00000000 ; used to terminate set-up tables 124 00000000 125 00000000 126 00000000 ; External bus interface register addresses 127 00000000 128 00000000 FFE00000 EBI_base EQU &FFE00000 129 00000000 130 00000000 00000000 EBI_CSR0 EQU &00 131 00000000 00000004 EBI_CSR1 EQU &04 ARM Macro Assembler Page 6 132 00000000 00000008 EBI_CSR2 EQU &08 133 00000000 0000000C EBI_CSR3 EQU &0C 134 00000000 00000010 EBI_CSR4 EQU &10 135 00000000 00000014 EBI_CSR5 EQU &14 136 00000000 00000018 EBI_CSR6 EQU &18 137 00000000 0000001C EBI_CSR7 EQU &1C 138 00000000 00000020 EBI_RCR EQU &20 139 00000000 00000024 EBI_MCR EQU &24 140 00000000 141 00000000 ; EBI CSR bit fields 142 00000000 00002000 CSEN EQU &00002000 ; Chip select enable 143 00000000 00001000 BAT EQU &00001000 ; Byte access type (byte sel ect) 144 00000000 00000200 TDF1 EQU &00000200 ; One data float cycle 145 00000000 00000400 TDF2 EQU &00000400 ; Two data float cycles 146 00000000 00000600 TDF3 EQU &00000600 ; Three data float cycles 147 00000000 00000800 TDF4 EQU &00000800 ; Four data float cycles 148 00000000 00000A00 TDF5 EQU &00000A00 ; Five data float cycles 149 00000000 00000C00 TDF6 EQU &00000C00 ; Six data float cycles 150 00000000 00000E00 TDF7 EQU &00000E00 ; Seven data float cycles 151 00000000 00000000 Pg1M EQU &00000000 ; 1 Mbyte pages 152 00000000 00000080 Pg4M EQU &00000080 ; 4 Mbyte pages 153 00000000 00000100 Pg16M EQU &00000100 ; 16 Mbyte pages 154 00000000 00000180 Pg64M EQU &00000180 ; 64 Mbyte pages 155 00000000 00000020 NWS1 EQU &00000020 ; 1 wait state (WSE included ) 156 00000000 00000024 NWS2 EQU &00000024 ; 2 wait states 157 00000000 00000028 NWS3 EQU &00000028 ; 3 wait states 158 00000000 0000002C ARM Macro Assembler Page 7 NWS4 EQU &0000002C ; 4 wait states 159 00000000 00000030 NWS5 EQU &00000030 ; 5 wait states 160 00000000 00000034 NWS6 EQU &00000034 ; 6 wait states 161 00000000 00000038 NWS7 EQU &00000038 ; 7 wait states 162 00000000 0000003C NWS8 EQU &0000003C ; 8 wait states 163 00000000 00000002 DBW8 EQU &00000002 ; 8-bit bus 164 00000000 00000001 DBW16 EQU &00000001 ; 16-bit bus 165 00000000 166 00000000 ; "Special function" register addresses 167 00000000 168 00000000 FFF00000 SF_base EQU &FFF00000 169 00000000 170 00000000 00000000 SF_CIDR EQU &00 171 00000000 00000004 SF_EXID EQU &04 172 00000000 00000008 SF_RSR EQU &08 173 00000000 0000000C SF_MMR EQU &0C 174 00000000 00000018 SF_PMR EQU &18 175 00000000 176 00000000 177 00000000 ; PIO register addresses 178 00000000 179 00000000 FFFF0000 PIO_base EQU &FFFF0000 180 00000000 181 00000000 00000000 PIO_PER EQU &00 182 00000000 00000004 PIO_PDR EQU &04 183 00000000 00000008 PIO_PSR EQU &08 184 00000000 00000010 PIO_OER EQU &10 185 00000000 00000014 PIO_ODR EQU &14 186 00000000 00000018 PIO_OSR EQU &18 187 00000000 00000020 PIO_IFER EQU &20 188 00000000 00000024 PIO_IFDR EQU &24 189 00000000 00000028 PIO_IFSR EQU &28 190 00000000 00000030 ARM Macro Assembler Page 8 PIO_SODR EQU &30 191 00000000 00000034 PIO_CODR EQU &34 192 00000000 00000038 PIO_ODSR EQU &38 193 00000000 0000003C PIO_PDSR EQU &3C 194 00000000 00000040 PIO_IER EQU &40 195 00000000 00000044 PIO_IDR EQU &44 196 00000000 00000048 PIO_IMR EQU &48 197 00000000 0000004C PIO_ISR EQU &4C 198 00000000 199 00000000 200 00000000 ; Power saving register addresses 201 00000000 202 00000000 FFFF4000 PS_base EQU &FFFF4000 203 00000000 204 00000000 00000000 PS_CR EQU &00 205 00000000 00000004 PS_PCER EQU &04 206 00000000 00000008 PS_PCDR EQU &08 207 00000000 0000000C PS_PCSR EQU &0C 208 00000000 209 00000000 210 00000000 ; Watchdog register addresses 211 00000000 212 00000000 FFFF8000 WD_base EQU &FFFF8000 213 00000000 214 00000000 00000000 WD_OMR EQU &00 215 00000000 00000004 WD_CMR EQU &04 216 00000000 00000008 WD_CR EQU &08 217 00000000 0000000C WD_SR EQU &0C 218 00000000 219 00000000 220 00000000 ; USART[0:1] register addresses 221 00000000 222 00000000 FFFD0000 US0_base EQU &FFFD0000 ; Serial port 0 223 00000000 FFFCC000 US1_base EQU &FFFCC000 ; Serial port 1 ARM Macro Assembler Page 9 224 00000000 225 00000000 00000000 US_CR EQU &00 226 00000000 00000004 US_MR EQU &04 227 00000000 00000008 US_IER EQU &08 228 00000000 0000000C US_IDR EQU &0C 229 00000000 00000010 US_IMR EQU &10 230 00000000 00000014 US_CSR EQU &14 231 00000000 00000018 US_RHR EQU &18 232 00000000 0000001C US_THR EQU &1C 233 00000000 00000020 US_BRGR EQU &20 234 00000000 00000024 US_RTOR EQU &24 235 00000000 00000028 US_TTGR EQU &28 236 00000000 00000030 US_RPR EQU &30 237 00000000 00000034 US_RCR EQU &34 238 00000000 00000038 US_TPR EQU &38 239 00000000 0000003C US_TCR EQU &3C 240 00000000 241 00000000 ; USART bit definitions 242 00000000 243 00000000 00000001 RxRdy EQU &001 ; Channel Status Register bi ts 244 00000000 00000002 TxRdy EQU &002 245 00000000 00000004 RxBrk EQU &004 246 00000000 00000008 EndRx EQU &008 247 00000000 00000010 EndTx EQU &010 248 00000000 00000020 OvrE EQU &020 249 00000000 00000040 FramE EQU &040 250 00000000 00000080 ParE EQU &080 251 00000000 00000100 Timeout EQU &100 252 00000000 00000200 TxEmpty EQU &200 253 00000000 254 00000000 255 00000000 ; Timer/Counter register addresses 256 00000000 ARM Macro Assembler Page 10 257 00000000 FFFE0000 TC_base EQU &FFFE0000 258 00000000 259 00000000 00000000 TC_CHL0 EQU &00 ; Base offset for TC0 260 00000000 00000040 TC_CHL1 EQU &40 ; Base offset for TC1 261 00000000 00000080 TC_CHL2 EQU &80 ; Base offset for TC2 262 00000000 000000C0 TC_BCR EQU &C0 ; Block control register 263 00000000 000000C4 TC_BMR EQU &C4 ; Block mode register 264 00000000 265 00000000 ; Register offsets within for TC 266 00000000 00000000 TC_CCR EQU &00 267 00000000 00000004 TC_CMR EQU &04 268 00000000 00000010 TC_CVR EQU &10 269 00000000 00000014 TC_RA EQU &14 270 00000000 00000018 TC_RB EQU &18 271 00000000 0000001C TC_RC EQU &1C 272 00000000 00000020 TC_SR EQU &20 273 00000000 00000024 TC_IER EQU &24 274 00000000 00000028 TC_IDR EQU &28 275 00000000 0000002C TC_IMR EQU &2C 276 00000000 277 00000000 278 00000000 ; Interrupt controller register addresses 279 00000000 280 00000000 FFFFF000 AIC_base EQU &FFFFF000 281 00000000 282 00000000 00000000 AIC_SMR0 EQU &00 ; Source mode/priority - FIQ 283 00000000 00000004 AIC_SMR1 EQU &04 ; Source mode/priority - Sof tware 284 00000000 00000008 AIC_SMR2 EQU &08 ; Source mode/priority - USA RT #0 285 00000000 0000000C AIC_SMR3 EQU &0C ; Source mode/priority - USA RT #1 ARM Macro Assembler Page 11 286 00000000 00000010 AIC_SMR4 EQU &10 ; Source mode/priority - Tim er #0 287 00000000 00000014 AIC_SMR5 EQU &14 ; Source mode/priority - Tim er #1 288 00000000 00000018 AIC_SMR6 EQU &18 ; Source mode/priority - Tim er #2 289 00000000 0000001C AIC_SMR7 EQU &1C ; Source mode/priority - Wat chdog 290 00000000 00000020 AIC_SMR8 EQU &20 ; Source mode/priority - PIO 291 00000000 00000040 AIC_SMR16 EQU &40 ; Source mode/priority - IRQ #0 (Spartan) 292 00000000 00000044 AIC_SMR17 EQU &44 ; Source mode/priority - IRQ #1 (Virtex) 293 00000000 00000048 AIC_SMR18 EQU &48 ; Source mode/priority - IRQ #2 (Ethernet) 294 00000000 295 00000000 00000080 AIC_SVR0 EQU &80 ; Source vector - FIQ 296 00000000 00000084 AIC_SVR1 EQU &84 ; Source vector - Software 297 00000000 00000088 AIC_SVR2 EQU &88 ; Source vector - USART #0 298 00000000 0000008C AIC_SVR3 EQU &8C ; Source vector - USART #1 299 00000000 00000090 AIC_SVR4 EQU &90 ; Source vector - Timer #0 300 00000000 00000094 AIC_SVR5 EQU &94 ; Source vector - Timer #1 301 00000000 00000098 AIC_SVR6 EQU &98 ; Source vector - Timer #2 302 00000000 0000009C AIC_SVR7 EQU &9C ; Source vector - Watchdog 303 00000000 000000A0 AIC_SVR8 ARM Macro Assembler Page 12 EQU &A0 ; Source vector - PIO 304 00000000 000000C0 AIC_SVR16 EQU &C0 ; Source vector - IRQ #0 (Sp artan) 305 00000000 000000C4 AIC_SVR17 EQU &C4 ; Source vector - IRQ #1 (Vi rtex) 306 00000000 000000C8 AIC_SVR18 EQU &C8 ; Source vector - IRQ #2 (Et hernet) 307 00000000 308 00000000 00000100 AIC_IVR EQU &100 ; Vector register (IRQ) 309 00000000 00000104 AIC_FVR EQU &104 ; Vector register (FIQ) 310 00000000 00000108 AIC_ISR EQU &108 ; Interrupt status 311 00000000 0000010C AIC_IPR EQU &10C ; (Potential) interrupts pen ding 312 00000000 00000110 AIC_IMR EQU &110 ; Interrupt mask 313 00000000 00000114 AIC_CISR EQU &114 ; Core IRQ/FIQ status 314 00000000 00000120 AIC_IECR EQU &120 ; Interrupt enable 315 00000000 00000124 AIC_IDCR EQU &124 ; Interrupt disable 316 00000000 00000128 AIC_ICCR EQU &128 ; Interrupt clear 317 00000000 0000012C AIC_ISCR EQU &12C ; Interrupt set 318 00000000 00000130 AIC_EOICR EQU &130 ; Signal end of interrupt 319 00000000 00000134 AIC_SPU EQU &134 ; Spurious interrupt vector 320 00000000 321 00000000 ;------------------------------------------------------- ----------------------- 322 00000000 ; `Magic' numbers used to derive baud rate divider from clock speed 323 00000000 324 00000000 0001D7DC baud115k2 EQU &0001D7DC ; 0.1152 * &10000 * 16 325 00000000 00009D49 baud38k4 EQU &00009D49 ; 0.0384 * &10000 * 16 326 00000000 00004EA5 baud19k2 ARM Macro Assembler Page 13 EQU &00004EA5 ; 0.0192 * &10000 * 16 327 00000000 00002752 baud9600 EQU &00002752 ; 0.0096 * &10000 * 16 328 00000000 329 00000000 ;------------------------------------------------------- ----------------------- 330 00000000 ; Local PIO bit definitions for AT91 board 331 00000000 332 00000000 00000200 AT91_Spartan_IRQ EQU &00000200 ; 333 00000000 00000400 AT91_Virtex_IRQ EQU &00000400 ; 334 00000000 00000800 AT91_Ether_IRQ EQU &00000800 ; 335 00000000 00001000 AT91_FIQ EQU &00001000 ; Open drain (Also HDC signa l) 336 00000000 337 00000000 00010000 AT91_Spartan_prog EQU &00010000 ; Active low 338 00000000 00020000 AT91_Virtex_prog EQU &00020000 ; Active low 339 00000000 00040000 AT91_Spartan_init EQU &00040000 ; Active low input 340 00000000 00080000 AT91_Virtex_init EQU &00080000 ; Active low input 341 00000000 342 00000000 00800000 AT91_Spartan_CS1 EQU &00800000 ; Also LCD_RS 343 00000000 00001000 AT91_Spartan_HDC EQU &00001000 ; Also FIQ signal 344 00000000 00002000 AT91_FPGA_baud EQU &00002000 ; Also DOUT - 345 00000000 ; driven low by Spartan at configuration time 346 00000000 347 00000000 00100000 AT91_LCD_light EQU &00100000 ; 348 00000000 349 00000000 00800000 AT91_LCD_RS EQU &00800000 ; Also Spartan CS1 350 00000000 01000000 AT91_LCD_En EQU &01000000 ; 351 00000000 02000000 AT91_LCD_RW ARM Macro Assembler Page 14 EQU &02000000 ; 352 00000000 353 00000000 40000000 AT91_LED_En EQU &40000000 ; 354 00000000 355 00000000 00000080 AT91_LCD_busy EQU &00000080 ; MSB of data bus 356 00000000 357 00000000 ;------------------------------------------------------- ----------------------- 358 00000000 359 00000000 00000000 prog_SA0_data EQU &0 ; XPIO register offsets 360 00000000 00000001 prog_SA0_ctrl EQU &1 361 00000000 00000002 prog_SA1_data EQU &2 362 00000000 00000003 prog_SA1_ctrl EQU &3 363 00000000 00000004 prog_SB0_data EQU &4 364 00000000 00000005 prog_SB0_ctrl EQU &5 365 00000000 00000006 prog_SB1_data EQU &6 366 00000000 00000007 prog_SB1_ctrl EQU &7 367 00000000 00000008 prog_VS0_data EQU &8 368 00000000 00000009 prog_VS0_ctrl EQU &9 369 00000000 0000000A prog_VS1_data EQU &A 370 00000000 0000000B prog_VS1_ctrl EQU &B 371 00000000 372 00000000 ;------------------------------------------------------- ----------------------- 373 00000000 END 16 00000000 ; GET link_addresses.s ; Addresses (etc.) of programmes 17 00000000 18 00000000 AREA flash, CODE, READONLY 19 00000000 ENTRY 20 00000000 ARM Macro Assembler Page 15 21 00000000 EA00001B Flash_prog B Flash_prog_start ; 22 00000004 23 00000004 ; Pack version & date into 32 bits 24 00000004 0000AD81 Version_ID DCD Maker*&1000000 + Version*&10000 + day*&8 00 + month*&80 + year 25 00000008 26 00000008 41 54 39 31 20 4F 66 66 2D 62 6F 61 72 64 20 46 6C 61 73 68 20 52 4F 4D 20 70 72 6F 67 72 61 6D 6D 65 72 20 76 65 72 73 69 6F 6E 20 30 2E 30 20 DCB "AT91 Off-board Flash ROM programmer ver sion 0.0 " 27 00000038 4A 2E 20 47 61 72 73 69 64 65 2C 20 28 63 29 20 55 6E 69 76 65 72 73 69 74 79 20 6F 66 20 4D 61 6E 63 68 65 73 74 65 72 20 DCB "J. Garside, (c) University of Mancheste r " 28 00000061 4E 6F 76 65 6D 62 65 72 20 32 30 30 31 DCB "November 2001" 29 0000006E 30 0000006E 00 00 ALIGN 31 00000070 32 00000070 33 00000070 FFFD0000 Prog_host_link DCD US0_base ; 34 00000074 35 00000074 36 00000074 Flash_prog_start ; Initialise things 37 00000074 38 00000074 ; adrl r0, XPIO_config ; Six PIOs ARM Macro Assembler Page 16 39 00000074 ; bl spartan_load ; Configure Spartan device 40 00000074 41 00000074 EB000154 bl XPIO_init ; Initialise PIO states 42 00000078 43 00000078 44 00000078 ; Set baud rates 45 00000078 ; Poll both UARTs to find first character with no errors 46 00000078 ; save pointer to it (R11) 47 00000078 ; Print appropriate message? 48 00000078 49 00000078 E3A09000 mov r9, #0 ; All addresses writeable 50 0000007C ; R10 not needed here 51 0000007C E51FB014 ldr r11, Prog_host_link ; Pointer to UART 52 00000080 53 00000080 GET fp1.s ; Main body of code 1 00000080 ;------------------------------------------------------- ----------------------- 2 00000080 ; Manchester University ARM/Xilinx board software 3 00000080 ; Flash ROM programming code 4 00000080 ; 5 00000080 ; J. Garside November 2001 6 00000080 7 00000080 ; To do: 8 00000080 ; Locking 9 00000080 10 00000080 11 00000080 ; Do not corrupt: 12 00000080 ; R9 contains lowest modifiable address 13 00000080 ; R10 contains base address (if needed) 14 00000080 ; R11 contains pointer to UART 15 00000080 16 00000080 00200000 flash_size EQU &00200000 ; 2 Mbytes 17 00000080 00004000 flash_protected EQU &00004000 ; 16 Kbytes - can't modify o wn ROM 18 00000080 ; Protects up to boot_table 19 00000080 20 00000080 00000800 Flash_load_buffer EQU &800 ; Safely above code if in RA M 21 00000080 00000010 Flash_comm_buff_len EQU 16 ; NB Reserve 18 bytes 22 00000080 23 00000080 02000000 Erase_timeout EQU &02000000 ; About 6s if ALL at 40MHz 24 00000080 00000120 Write_timeout EQU &120 ; 50us if ALL at 40MHz 25 00000080 26 00000080 27 00000080 FEA51B1E Flash_Challenge ARM Macro Assembler Page 17 EQU &FEA51B1E ; 28 00000080 FEE1900D Flash_Response EQU &FEE1900D ; 29 00000080 30 00000080 ;------------------------------------------------------- ----------------------- 31 00000080 32 00000080 33 00000080 EB0000F3 Flash_check bl Prog_Host_in ; Get first byte 34 00000084 E35000FE cmp r0, #(Flash_Challenge :SHR: 24) :AND: &F F 35 00000088 1AFFFFFC bne Flash_check ; Fail, keep listening 36 0000008C EB0000F0 bl Prog_Host_in ; Get second byte 37 00000090 E35000A5 cmp r0, #(Flash_Challenge :SHR: 16) :AND: &F F 38 00000094 1AFFFFF9 bne Flash_check ; 39 00000098 EB0000ED bl Prog_Host_in ; etc. 40 0000009C E350001B cmp r0, #(Flash_Challenge :SHR: 8) :AND: &FF 41 000000A0 1AFFFFF6 bne Flash_check ; 42 000000A4 EB0000EA bl Prog_Host_in ; 43 000000A8 E350001E cmp r0, #Flash_Challenge :AND: &FF 44 000000AC 1AFFFFF3 bne Flash_check ; 45 000000B0 46 000000B0 E3A000FE mov r0, #(Flash_Response :SHR: 24) :AND: &FF 47 000000B4 EB0000E0 bl Prog_Host_out ; Send reply ... 48 000000B8 E3A000E1 mov r0, #(Flash_Response :SHR: 16) :AND: &FF 49 000000BC EB0000DE bl Prog_Host_out ; 50 000000C0 E3A00090 mov r0, #(Flash_Response :SHR: 8) :AND: &FF 51 000000C4 EB0000DC bl Prog_Host_out ; 52 000000C8 E3A0000D mov r0, #Flash_Response :AND: &FF 53 000000CC EB0000DA bl Prog_Host_out ; 54 000000D0 55 000000D0 56 000000D0 EB0000DF prog_loop bl Prog_Host_in ; Get command 57 000000D4 58 000000D4 E200007F and r0, r0, #&7F ; Clumsy dispatcher! 59 000000D8 E3500052 cmp r0, #"R" ; 60 000000DC 0A00000D beq prog_read ; 61 000000E0 E3500057 cmp r0, #"W" ; 62 000000E4 0A00001E beq prog_write ; (Programme) 63 000000E8 E3500045 cmp r0, #"E" ; 64 000000EC 0A00005D beq prog_erase ; 65 000000F0 E3500050 cmp r0, #"P" ; 66 000000F4 0A000083 beq prog_ping ; 67 000000F8 E350004C cmp r0, #"L" ; 68 000000FC 0A000084 beq prog_lockout ; 69 00000100 E3500043 cmp r0, #"C" ; 70 00000104 0A000084 beq prog_check_lock ; 71 00000108 E3500049 cmp r0, #"I" ; 72 0000010C 0A00008C beq prog_dev_ID ; 73 00000110 ; Else not recognised 74 00000110 EB0000C9 bl Prog_Host_out ; Echo character 75 00000114 EAFFFFED b prog_loop ; 76 00000118 ARM Macro Assembler Page 18 77 00000118 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 78 00000118 79 00000118 EB000090 prog_read bl Prog_Host_get_word ; 80 0000011C E1A01000 mov r1, r0 ; Address 81 00000120 EB00008E bl Prog_Host_get_word ; 82 00000124 E1B02000 movs r2, r0 ; Length 83 00000128 0A00000B beq prog_read_out ; Quit if zero bytes 84 0000012C 85 0000012C E3A03010 prog_read_1 mov r3, #Flash_comm_buff_len ; 86 00000130 87 00000130 EB0000FF prog_read_2 bl flash_r_byte ; Get byte 88 00000134 E2811001 add r1, r1, #1 ; Increment address 89 00000138 EB0000BF bl Prog_Host_out ; Send character 90 0000013C 91 0000013C E2522001 subs r2, r2, #1 ; Overall count 92 00000140 0A000005 beq prog_read_out ; All done - exit 93 00000144 E2533001 subs r3, r3, #1 ; Count on this `line' 94 00000148 8AFFFFF8 bhi prog_read_2 ; Repeat <= "Flash_comm_buff _len" 95 0000014C ; times 96 0000014C EB0000C0 bl Prog_Host_in ; Then await an "A" 97 00000150 E3500041 cmp r0, #"A" ; 98 00000154 0AFFFFF4 beq prog_read_1 ; Another buffer load 99 00000158 EAFFFFDC b prog_loop ; or give up! 100 0000015C 101 0000015C EB0000BC prog_read_out bl Prog_Host_in ; Then await an "A" (etc.) 102 00000160 EAFFFFDA b prog_loop ; 103 00000164 104 00000164 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 105 00000164 ; Write a sequence to the Flash 106 00000164 ; No real verification included 107 00000164 108 00000164 EB00007D prog_write bl Prog_Host_get_word ; Programme flash 109 00000168 E1A01000 mov r1, r0 ; Address 110 0000016C EB00007B bl Prog_Host_get_word ; 111 00000170 E1B02000 movs r2, r0 ; Length 112 00000174 0A000030 beq prog_write_out ; Quit if zero bytes 113 00000178 114 00000178 E3A0004E mov r0, #"N" ; Not a real acknowledge 115 0000017C E1510009 cmp r1, r9 ; Protected area at bottom 116 00000180 3A000030 blo prog_write_error ; 117 00000184 E0813002 add r3, r1, r2 ; Find last address 118 00000188 E3530602 cmp r3, #flash_size ; 2Mbyte flash size 119 0000018C 8A00002D bhi prog_write_error ; 120 00000190 121 00000190 E1A06001 mov r6, r1 ; Copy of address (in case o ARM Macro Assembler Page 19 dd) 122 00000194 E3160001 tst r6, #1 ; Odd address? 123 00000198 0A000003 beq prog_write_1 ; no 124 0000019C 125 0000019C E3C11001 bic r1, r1, #1 ; Deal with odd start addres s 126 000001A0 E3A04B02 mov r4, #Flash_load_buffer ; Temp. buffer space 127 000001A4 EB0000E2 bl flash_r_byte ; Read previous address [R1] 128 000001A8 E5C40000 strb r0, [r4] ; into first buffer locatio n 129 000001AC 130 000001AC 131 000001AC E3A04B02 prog_write_1 mov r4, #Flash_load_buffer ; Temp. buffer space 132 000001B0 E3A03010 mov r3, #Flash_comm_buff_len ; 133 000001B4 134 000001B4 E3160001 tst r6, #1 ; Odd address? 135 000001B8 12844001 addne r4, r4, #1 ; yes - start one place in 136 000001BC 137 000001BC EB0000A4 prog_write_2 bl Prog_Host_in ; Get byte 138 000001C0 E4C40001 strb r0, [r4], #1 ; Save byte 139 000001C4 140 000001C4 E2522001 subs r2, r2, #1 ; Total count 141 000001C8 0A00000E beq prog_write_tidy ; Got last one 142 000001CC E2533001 subs r3, r3, #1 ; Line count 143 000001D0 8AFFFFF9 bhi prog_write_2 ; Repeat <= through buffer 144 000001D4 145 000001D4 E3A04B02 mov r4, #Flash_load_buffer ; Temp. buffer space 146 000001D8 E3A03008 mov r3, #Flash_comm_buff_len/2 ; Now in half words 147 000001DC 148 000001DC E0D400B2 prog_write_3 ldrh r0, [r4], #2 ; 149 000001E0 EB000068 bl flash_write ; No verification yet @@@ 150 000001E4 151 000001E4 E2811002 add r1, r1, #2 ; Destination address 152 000001E8 E2533001 subs r3, r3, #1 ; 153 000001EC 8AFFFFFA bhi prog_write_3 ; Buffer output loop 154 000001F0 155 000001F0 E3160001 tst r6, #1 ; Odd start address? 156 000001F4 15D40000 ldrneb r0, [r4] ; then move last byte to st art 157 000001F8 15440010 strneb r0, [r4, #-Flash_comm_buff_len] 158 000001FC ; Next pass must get this one 159 000001FC 160 000001FC E3A00041 mov r0, #"A" ; 161 00000200 EB00008D bl Prog_Host_out ; Send Acknowledge 162 00000204 EAFFFFE8 b prog_write_1 ; and repeat 163 00000208 164 00000208 E2443B02 ARM Macro Assembler Page 20 prog_write_tidy sub r3, r4, #Flash_load_buffer ; Count remaindered bytes 165 0000020C E3130001 tst r3, #1 ; Odd end address 166 00000210 13A000FF movne r0, #&FF ; if so, pad with FF 167 00000214 15C40000 strneb r0, [r4] ; (Does no damage & not test ed for) 168 00000218 12833001 addne r3, r3, #1 ; 169 0000021C 170 0000021C E1B030A3 movs r3, r3, lsr #1 ; Now in half words 171 00000220 0A000005 beq prog_write_out ; None extra 172 00000224 173 00000224 E3A04B02 mov r4, #Flash_load_buffer ; Temp. buffer space 174 00000228 175 00000228 E0D400B2 prog_write_4 ldrh r0, [r4], #2 ; 176 0000022C EB000055 bl flash_write ; No verification yet @@@ 177 00000230 178 00000230 E2811002 add r1, r1, #2 ; Destination address 179 00000234 E2533001 subs r3, r3, #1 ; 180 00000238 8AFFFFFA bhi prog_write_4 ; Buffer output loop (II) 181 0000023C 182 0000023C E3A00041 prog_write_out mov r0, #"A" ; 183 00000240 EB00007D bl Prog_Host_out ; Send Acknowledge 184 00000244 EAFFFFA1 b prog_loop ; and relax! 185 00000248 186 00000248 prog_write_error 187 00000248 E3520010 cmp r2, #Flash_comm_buff_len ; Must be at least one byte 188 0000024C 83A02010 movhi r2, #Flash_comm_buff_len ; Only accept one `line' 189 00000250 190 00000250 prog_write_error1 191 00000250 EB00007F bl Prog_Host_in ; Get byte 192 00000254 E2522001 subs r2, r2, #1 ; 193 00000258 8AFFFFFC bhi prog_write_error1 ; Repeat for `line' 194 0000025C 195 0000025C E3A0004E mov r0, #"N" ; 196 00000260 EB000075 bl Prog_Host_out ; Send Non-acknowledge 197 00000264 EAFFFF99 b prog_loop ; and relax! 198 00000268 199 00000268 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 200 00000268 ; Erase block 201 00000268 ; Does not check block for blank; 202 00000268 ; such would need table of block sizes for different de vices. 203 00000268 204 00000268 EB00003C prog_erase bl Prog_Host_get_word ; 205 0000026C E1A02000 mov r2, r0 ; Address into R2 206 00000270 207 00000270 E3A0004E mov r0, #"N" ; Not a real acknowledge 208 00000274 E1520009 cmp r2, r9 ; Protected area ARM Macro Assembler Page 21 209 00000278 3A000020 blo prog_erase_error ; 210 0000027C E3520602 cmp r2, #flash_size ; 2Mbyte flash size 211 00000280 2A00001E bhs prog_erase_error ; Address too big 212 00000284 213 00000284 E3A000AA mov r0, #&AA ; Data #1 214 00000288 E3A01055 mov r1, #&55 ; Address 215 0000028C E3811C55 orr r1, r1, #&5500 ; 216 00000290 E1A01081 mov r1, r1, lsl #1 ; Flash A0 is our A1 217 00000294 EB000089 bl flash_w_hword ; 218 00000298 219 00000298 E3A00055 mov r0, #&55 ; Data #2 220 0000029C E3A010AA mov r1, #&AA ; Address 221 000002A0 E3811C2A orr r1, r1, #&2A00 ; 222 000002A4 E1A01081 mov r1, r1, lsl #1 ; Flash A0 is our A1 223 000002A8 EB000084 bl flash_w_hword ; 224 000002AC 225 000002AC E3A00080 mov r0, #&80 ; Data #3 226 000002B0 E3A01055 mov r1, #&55 ; Address 227 000002B4 E3811C55 orr r1, r1, #&5500 ; 228 000002B8 E1A01081 mov r1, r1, lsl #1 ; Flash A0 is our A1 229 000002BC EB00007F bl flash_w_hword ; 230 000002C0 231 000002C0 E3A000AA mov r0, #&AA ; Data #4 232 000002C4 EB00007D bl flash_w_hword ; 233 000002C8 234 000002C8 E3A00055 mov r0, #&55 ; Data #5 235 000002CC E3A010AA mov r1, #&AA ; Address 236 000002D0 E3811C2A orr r1, r1, #&2A00 ; 237 000002D4 E1A01081 mov r1, r1, lsl #1 ; Flash A0 is our A1 238 000002D8 EB000078 bl flash_w_hword ; 239 000002DC 240 000002DC E1A01002 mov r1, r2 ; Restore address to R1 241 000002E0 E3A00030 mov r0, #&30 ; Data #6 242 000002E4 EB000075 bl flash_w_hword ; 243 000002E8 244 000002E8 E3A000FF mov r0, #&FF ; Expected value 245 000002EC E3A05402 mov r5, #Erase_timeout ; 246 000002F0 EB00005D bl flash_wtr ; Could check R5 for timeout 247 000002F4 248 000002F4 E1150005 tst r5, r5 ; 249 000002F8 03A0004E moveq R0, #"N" ; Timeout indicated 250 000002FC 13A00041 movne r0, #"A" ; Acknowledge if no timeout 251 00000300 252 00000300 prog_erase_error 253 00000300 EB00004D bl Prog_Host_out ; Timeout is not, necessar ily 254 00000304 EAFFFF71 b prog_loop ; the only fault. 255 00000308 256 00000308 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 257 00000308 258 00000308 E3A00041 prog_ping mov r0, #"A" ; Just Acknowledge 259 0000030C EB00004A bl Prog_Host_out ; 260 00000310 EAFFFF6E b prog_loop ; 261 00000314 262 00000314 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - ARM Macro Assembler Page 22 - - - - - - - - - - - - 263 00000314 264 00000314 prog_lockout ; Nothing for now @@@ 265 00000314 EB000048 bl Prog_Host_out ; Echo character @@@ 266 00000318 EAFFFF6C b prog_loop ; 267 0000031C 268 0000031C ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 269 0000031C 270 0000031C EB00000F prog_check_lock bl Prog_Host_get_word ; 271 00000320 E3C010FF bic r1, r0, #&FF ; Address 272 00000324 E3C11C1F bic r1, r1, #&1F00 ; Clear (most) lower bits 273 00000328 E3811004 orr r1, r1, #4 ; Lockout check 274 0000032C EB00002B bl flash_ID ; 275 00000330 E3100001 tst r0, #1 ; 276 00000334 03A0004E moveq r0, #"N" ; Not locked 277 00000338 13A0004C movne r0, #"L" ; Locked 278 0000033C EB00003E bl Prog_Host_out ; 279 00000340 EAFFFF62 b prog_loop ; 280 00000344 281 00000344 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 282 00000344 283 00000344 E3A01000 prog_dev_ID mov r1, #0 ; Manufacturer code 284 00000348 EB000024 bl flash_ID ; 285 0000034C EB00003A bl Prog_Host_out ; 286 00000350 287 00000350 E3A01002 mov r1, #2 ; Part code 288 00000354 EB000021 bl flash_ID ; 289 00000358 EB000037 bl Prog_Host_out ; 290 0000035C 291 0000035C EAFFFF5B b prog_loop ; 292 00000360 293 00000360 ;------------------------------------------------------- ----------------------- 294 00000360 295 00000360 Prog_Host_get_word 296 00000360 E92D4002 stmfd sp!, {r1,lr} ; 297 00000364 EB00003A bl Prog_Host_in ; 298 00000368 E1A01000 mov r1, r0 ; 299 0000036C EB000038 bl Prog_Host_in ; 300 00000370 E1811400 orr r1, r1, r0, lsl #8 ; 301 00000374 EB000036 bl Prog_Host_in ; 302 00000378 E1811800 orr r1, r1, r0, lsl #16 ; 303 0000037C EB000034 bl Prog_Host_in ; 304 00000380 E1810C00 orr r0, r1, r0, lsl #24 ; 305 00000384 E8BD8002 ldmfd sp!, {r1,pc} ; 306 00000388 307 00000388 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 308 00000388 ; Remote flash memory write routine 309 00000388 ; Halfword data in R0, address in R1 310 00000388 ; On exit R5 = 0 indicates timeout; R5 <> 0 indicates (p robably) okay ARM Macro Assembler Page 23 311 00000388 312 00000388 E92D400F flash_write stmfd sp!, {r0-r3, lr} ; 313 0000038C 314 0000038C E3A000AA mov r0, #&AA ; Data #1 315 00000390 E3A01055 mov r1, #&55 ; Address 316 00000394 E3811C55 orr r1, r1, #&5500 ; 317 00000398 E1A01081 mov r1, r1, lsl #1 ; Flash A0 is our A1 318 0000039C EB000047 bl flash_w_hword ; 319 000003A0 320 000003A0 E3A00055 mov r0, #&55 ; Data #2 321 000003A4 E3A010AA mov r1, #&AA ; Address 322 000003A8 E3811C2A orr r1, r1, #&2A00 ; 323 000003AC E1A01081 mov r1, r1, lsl #1 ; Flash A0 is our A1 324 000003B0 EB000042 bl flash_w_hword ; 325 000003B4 326 000003B4 E3A000A0 mov r0, #&A0 ; Data #3 327 000003B8 E3A01055 mov r1, #&55 ; Address 328 000003BC E3811C55 orr r1, r1, #&5500 ; 329 000003C0 E1A01081 mov r1, r1, lsl #1 ; Flash A0 is our A1 330 000003C4 EB00003D bl flash_w_hword ; 331 000003C8 332 000003C8 E89D0003 ldmfd sp, {r0-r1} ; Restore data (NOT a pop) 333 000003CC EB00003B bl flash_w_hword ; 334 000003D0 335 000003D0 E20000FF and r0, r0, #&FF ; Just test one byte 336 000003D4 E3A05E12 mov r5, #Write_timeout ; 337 000003D8 EB000023 bl flash_wtr ; Wait for written (or timeo ut) 338 000003DC 339 000003DC E8BD800F ldmfd sp!, {r0-r3, pc} ; 340 000003E0 341 000003E0 ;; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 342 000003E0 ;; Substitutes for monitor read routines to remote flash 343 000003E0 ; 344 000003E0 ;flash_read_w stmfd sp!, {r0, r2-r3, lr} ; 345 000003E0 ; bic r2, r2, #3 ; Align anyway 346 000003E0 ; mov r3, #0 ; Accumulator 347 000003E0 ; mov r1, r2 ; Address 348 000003E0 ;1 bl flash_r_byte ; Fetch R0 349 000003E0 ; orr r3, r0, r3, ror #8 ; Data into acc. 350 000003E0 ; add r1, r1, #1 ; Inc. address 351 000003E0 ; tst r1, #3 ; Bottom addr. bits clear again? 352 000003E0 ; bne %b1 ; no 353 000003E0 ; mov r1, r3, ror #8 ; Realign for output 354 000003E0 ; ldmfd sp!, {r0, r2-r3, pc} ; 355 000003E0 ; 356 000003E0 ;flash_read_b stmfd sp!, {r0, lr} ; 357 000003E0 ; mov r1, r2 ; Address 358 000003E0 ; bl flash_r_byte ; 359 000003E0 ; mov r1, r0 ; Data 360 000003E0 ; ldmfd sp!, {r0, pc} ; 361 000003E0 362 000003E0 ;------------------------------------------------------- ----------------------- 363 000003E0 ; Read flash ID from address R1 into R0 ARM Macro Assembler Page 24 364 000003E0 ; 00000 = Manufacturer 365 000003E0 ; 00002 = Part code 366 000003E0 ; xx004 = Sector lockout state 367 000003E0 368 000003E0 E92D400E flash_ID stmfd sp!, {r1-r3, lr} ; 369 000003E4 370 000003E4 E3A000AA mov r0, #&AA ; Data #1 371 000003E8 E3A01055 mov r1, #&55 ; Address 372 000003EC E3811C55 orr r1, r1, #&5500 ; 373 000003F0 E1A01081 mov r1, r1, lsl #1 ; Flash A0 is our A1 374 000003F4 EB000031 bl flash_w_hword ; 375 000003F8 376 000003F8 E3A00055 mov r0, #&55 ; Data #2 377 000003FC E3A010AA mov r1, #&AA ; Address 378 00000400 E3811C2A orr r1, r1, #&2A00 ; 379 00000404 E1A01081 mov r1, r1, lsl #1 ; Flash A0 is our A1 380 00000408 EB00002C bl flash_w_hword ; 381 0000040C 382 0000040C E3A00090 mov r0, #&90 ; Data #3 383 00000410 E3A01055 mov r1, #&55 ; Address 384 00000414 E3811C55 orr r1, r1, #&5500 ; 385 00000418 E1A01081 mov r1, r1, lsl #1 ; Flash A0 is our A1 386 0000041C EB000027 bl flash_w_hword ; 387 00000420 388 00000420 E89D0002 ldmfd sp, {r1} ; Restore R1 (address) 389 00000424 390 00000424 EB000042 bl flash_r_byte ; 391 00000428 E1A01000 mov r1, r0 ; Keep answer 392 0000042C 393 0000042C E3A000F0 mov r0, #&F0 ; Leave ID mode 394 00000430 EB000022 bl flash_w_hword ; Address irrelevant 395 00000434 396 00000434 E1A00001 mov r0, r1 ; Reorganise registers 397 00000438 E8BD800E ldmfd sp!, {r1-r3, pc} ; 398 0000043C 399 0000043C ;------------------------------------------------------- ----------------------- 400 0000043C 401 0000043C END 54 0000043C 55 0000043C ;------------------------------------------------------- ----------------------- 56 0000043C ;------------------------------------------------------- ----------------------- 57 0000043C ; Send character in R0 to serial line #0 58 0000043C 59 0000043C E92D4004 Prog_Host_out stmfd sp!, {r2, lr} ; 60 00000440 61 00000440 E59B2014 Prog_Host_out1 ldr r2, [r11, #US_CSR] ; Pass byte to transm it in R0 62 00000444 E3120002 tst r2, #TxRdy ; Test if ready to transmit 63 00000448 0AFFFFFC beq Prog_Host_out1 ; 64 0000044C ARM Macro Assembler Page 25 65 0000044C E58B001C Prog_Host_out2 str r0, [r11, #US_THR] ; Send character 66 00000450 E8BD8004 ldmfd sp!, {r2, pc} ; 67 00000454 68 00000454 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 69 00000454 ; Get character from serial line #0 into R0 70 00000454 71 00000454 E92D4000 Prog_Host_in stmfd sp!, {lr} ; 72 00000458 73 00000458 E59B0014 Prog_Host_in1 ldr r0, [r11, #US_CSR] ; 74 0000045C E3100001 tst r0, #RxRdy ; Receiver ready? 75 00000460 0AFFFFFC beq Prog_Host_in1 ; 76 00000464 77 00000464 E59B0018 Prog_Host_in_rdy ldr r0, [r11, #US_RHR] ; Upper bits read as 0 78 00000468 E8BD8000 ldmfd sp!, {pc} ; Return byte in r0 79 0000046C 80 0000046C ;------------------------------------------------------- ----------------------- 81 0000046C ; Wait for addressed location/R1 to contain R0 82 0000046C ; Timeout count in R5 83 0000046C ; Returns R5 = 0 if timeout, else R5 <> 0 84 0000046C ; Corrupts R2, R3 85 0000046C 86 0000046C E59F31A8 flash_wtr ldr r3, SLit_Spartan_base ; Point at PIO 87 00000470 88 00000470 E3A020FF mov r2, #&FF ; Data bus to input 89 00000474 E5C32005 strb r2, [r3, #prog_SB0_ctrl] ; Low byte 90 00000478 E5C32009 strb r2, [r3, #prog_VS0_ctrl] ; High byte 91 0000047C 92 0000047C E5D32002 ldrb r2, [r3, #prog_SA1_data] ; 93 00000480 E3C22002 bic r2, r2, #&02 ; Assert nCS 94 00000484 E5C32002 strb r2, [r3, #prog_SA1_data] ; 95 00000488 96 00000488 E5D32000 ldrb r2, [r3, #prog_SA0_data] ; 97 0000048C E3C22020 bic r2, r2, #&20 ; Assert nOE 98 00000490 E5C32000 strb r2, [r3, #prog_SA0_data] ; 99 00000494 100 00000494 E5D32004 flash_wtr1 ldrb r2, [r3, #prog_SB0_data] ; 101 00000498 E2555001 subs r5, r5, #1 ; Decrement timeout 102 0000049C 11520000 cmpne r2, r0 ; 103 000004A0 1AFFFFFB bne flash_wtr1 ; Wait for values to match 104 000004A4 105 000004A4 E5D32000 ldrb r2, [r3, #prog_SA0_data] ; 106 000004A8 E3822020 orr r2, r2, #&20 ; Remove nOE 107 000004AC E5C32000 strb r2, [r3, #prog_SA0_data] ; 108 000004B0 ARM Macro Assembler Page 26 109 000004B0 E5D32002 ldrb r2, [r3, #prog_SA1_data] ; 110 000004B4 E3822002 orr r2, r2, #&02 ; Remove nCS 111 000004B8 E5C32002 strb r2, [r3, #prog_SA1_data] ; 112 000004BC 113 000004BC E1A0F00E mov pc, lr ; 114 000004C0 115 000004C0 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 116 000004C0 117 000004C0 E92D400F flash_w_hword stmfd sp!, {r0-r3, lr} ; 118 000004C4 119 000004C4 E59F3150 ldr r3, SLit_Spartan_base ; Point at PIO 120 000004C8 121 000004C8 E5C30004 strb r0, [r3, #prog_SB0_data] ; Data to output latches 122 000004CC E1A00420 mov r0, r0, lsr #8 ; High byte 123 000004D0 E5C30008 strb r0, [r3, #prog_VS0_data] ; 124 000004D4 125 000004D4 E3A0003B mov r0, #&3B ; Control inactive 126 000004D8 E5C30000 strb r0, [r3, #prog_SA0_data] ; 127 000004DC 128 000004DC E3A00000 mov r0, #&00 ; Data bus to output 129 000004E0 E5C30005 strb r0, [r3, #prog_SB0_ctrl] ; Low byte 130 000004E4 E5C30009 strb r0, [r3, #prog_VS0_ctrl] ; High byte 131 000004E8 132 000004E8 E3A02008 mov r2, #8 ; Reverse in bytes 133 000004EC 134 000004EC E1A000A1 mov r0, r1, lsr #1 ; A0 is not interesting 135 000004F0 EB00002C bl bit_rev ; A[8:1] 136 000004F4 E5C30006 strb r0, [r3, #prog_SB1_data] ; 137 000004F8 138 000004F8 E1A004A1 mov r0, r1, lsr #9 ; 139 000004FC EB000029 bl bit_rev ; A[16:9] 140 00000500 E5C3000A strb r0, [r3, #prog_VS1_data] 141 00000504 142 00000504 E1A008A1 mov r0, r1, lsr #17 ; 143 00000508 EB000026 bl bit_rev ; A[21:17] 144 0000050C E20000F8 and r0, r0, #&F8 ; Ensure upper bits clear 145 00000510 E3800001 orr r0, r0, #&01 ; Don't pulse reset 146 00000514 E5C30002 strb r0, [r3, #prog_SA1_data] ; nCS asserted 147 00000518 148 00000518 E3A0202B mov r2, #&2B ; Assert nWE 149 0000051C E5C32000 strb r2, [r3, #prog_SA0_data] ; 150 00000520 E3A0203B mov r2, #&3B ; Remove nWE 151 00000524 E5C32000 strb r2, [r3, #prog_SA0_data] ; 152 00000528 153 00000528 E3800002 orr r0, r0, #&02 ; nCS 154 0000052C E5C30002 strb r0, [r3, #prog_SA1_data] ; nCS removed 155 00000530 156 00000530 E8BD800F ldmfd sp!, {r0-r3, pc} ; 157 00000534 158 00000534 159 00000534 ; Internal 160 00000534 ; strh r0, [r10, r1] 161 00000534 162 00000534 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ARM Macro Assembler Page 27 163 00000534 ; Remote flash memory read routine 164 00000534 ; Byte data into R0, address in R1 165 00000534 166 00000534 E92D400E flash_r_byte stmfd sp!, {r1-r3, lr} ; 167 00000538 168 00000538 E59F30DC ldr r3, SLit_Spartan_base ; Point at PIO 169 0000053C 170 0000053C E3A0003B mov r0, #&3B ; Control inactive 171 00000540 E5C30000 strb r0, [r3, #prog_SA0_data] ; 172 00000544 173 00000544 E3A000FF mov r0, #&FF ; Data bus to input 174 00000548 E5C30005 strb r0, [r3, #prog_SB0_ctrl] ; Low byte 175 0000054C E5C30009 strb r0, [r3, #prog_VS0_ctrl] ; High byte 176 00000550 177 00000550 E3A02008 mov r2, #8 ; Reverse in bytes 178 00000554 179 00000554 E1A000A1 mov r0, r1, lsr #1 ; A0 is not interesting 180 00000558 EB000012 bl bit_rev ; A[8:1] 181 0000055C E5C30006 strb r0, [r3, #prog_SB1_data] ; 182 00000560 183 00000560 E1A004A1 mov r0, r1, lsr #9 ; 184 00000564 EB00000F bl bit_rev ; A[16:9] 185 00000568 E5C3000A strb r0, [r3, #prog_VS1_data] 186 0000056C 187 0000056C E1A008A1 mov r0, r1, lsr #17 ; 188 00000570 EB00000C bl bit_rev ; A[21:17] 189 00000574 190 00000574 E3110001 tst r1, #1 ; Odd or even byte? 191 00000578 192 00000578 E20000F8 and r0, r0, #&F8 ; Ensure upper bits clear 193 0000057C E3801001 orr r1, r0, #&01 ; Don't pulse reset 194 00000580 E5C31002 strb r1, [r3, #prog_SA1_data] ; nCS asserted 195 00000584 196 00000584 E3A0201B mov r2, #&1B ; Assert nOE 197 00000588 E5C32000 strb r2, [r3, #prog_SA0_data] ; 198 0000058C 199 0000058C 05D30004 ldreqb r0, [r3, #prog_SB0_data] ; Even byte 200 00000590 15D30008 ldrneb r0, [r3, #prog_VS0_data] ; or odd byte 201 00000594 202 00000594 E3A0203B mov r2, #&3B ; Remove nOE 203 00000598 E5C32000 strb r2, [r3, #prog_SA0_data] ; 204 0000059C 205 0000059C E3811002 orr r1, r1, #&02 ; nCS 206 000005A0 E5C31002 strb r1, [r3, #prog_SA1_data] ; nCS removed 207 000005A4 208 000005A4 E8BD800E ldmfd sp!, {r1-r3, pc} ; 209 000005A8 210 000005A8 ; Internal 211 000005A8 ; ldrb r0, [r10, r1] 212 000005A8 213 000005A8 214 000005A8 ;------------------------------------------------------- ----------------------- 215 000005A8 ; 216 000005A8 ;flash_ID_call ldr r3, SLit_Spartan_base ; Point at PIO 217 000005A8 ; 218 000005A8 ; mov r2, #8 ; Reverse in bytes ARM Macro Assembler Page 28 219 000005A8 ; 220 000005A8 ; mov r0, r1, lsr #1 ; A0 is not interesting 221 000005A8 ; bl bit_rev ; A[8:1] 222 000005A8 ; strb r0, [r3, #prog_SB1_data]; 223 000005A8 ; 224 000005A8 ; mov r0, r1, lsr #9 ; 225 000005A8 ; bl bit_rev ; A[16:9] 226 000005A8 ; strb r0, [r3, #prog_VS1_data] 227 000005A8 ; 228 000005A8 ; mov r0, r1, lsr #17 ; 229 000005A8 ; bl bit_rev ; A[21:17] 230 000005A8 ; and r0, r0, #&F8 ; Ensure upper bits clear 231 000005A8 ; orr r0, r0, #&03 ; Don't pulse reset 232 000005A8 ; strb r0, [r3, #prog_SA1_data]; No nCS yet 233 000005A8 ; 234 000005A8 ; mov r2, #&FF ; Data bus to input 235 000005A8 ; strb r2, [r3, #prog_SB0_ctrl]; Low byte 236 000005A8 ; strb r2, [r3, #prog_VS0_ctrl]; High byte 237 000005A8 ; 238 000005A8 ; ldrb r2, [r3, #prog_SA1_data]; 239 000005A8 ; bic r2, r2, #&02 ; Assert nCS 240 000005A8 ; strb r2, [r3, #prog_SA1_data]; 241 000005A8 ; 242 000005A8 ; ldrb r2, [r3, #prog_SA0_data]; 243 000005A8 ; bic r2, r2, #&20 ; Assert nOE 244 000005A8 ; strb r2, [r3, #prog_SA0_data]; 245 000005A8 ; 246 000005A8 ; ldrb r1, [r3, #prog_SB0_data]; Return this value 247 000005A8 ; 248 000005A8 ; ldrb r2, [r3, #prog_SA0_data]; 249 000005A8 ; orr r2, r2, #&20 ; Remove nOE 250 000005A8 ; strb r2, [r3, #prog_SA0_data]; 251 000005A8 ; 252 000005A8 ; ldrb r2, [r3, #prog_SA1_data]; 253 000005A8 ; orr r2, r2, #&02 ; Remove nCS 254 000005A8 ; strb r2, [r3, #prog_SA1_data]; 255 000005A8 ; 256 000005A8 ; mov pc, lr ; 257 000005A8 ; 258 000005A8 ;------------------------------------------------------- ----------------------- 259 000005A8 260 000005A8 E92D0006 bit_rev stmfd sp!, {r1, r2} ; Bit reverse lower R2 bit s in R0 261 000005AC E3A01000 mov r1, #0 ; Accumulator 262 000005B0 263 000005B0 E1B000A0 bit_rev1 movs r0, r0, lsr #1 ; LSB into carry 264 000005B4 E0A11001 adc r1, r1, r1 ; Shift left from carry 265 000005B8 E2522001 subs r2, r2, #1 ; 266 000005BC 8AFFFFFB bhi bit_rev1 ; 267 000005C0 268 000005C0 E1A00001 mov r0, r1 ; 269 000005C4 270 000005C4 E8BD0006 ldmfd sp!, {r1, r2} ; 271 000005C8 E1A0F00E mov pc, lr ; 272 000005CC ARM Macro Assembler Page 29 273 000005CC ;------------------------------------------------------- ----------------------- 274 000005CC ; Temporary routine for initialising Spartan device (as 6 PIOs) for 275 000005CC ; remote flash ROM reading, writing and erasing 276 000005CC 277 000005CC E92D0003 XPIO_init stmfd sp!, {r0, r1} ; 278 000005D0 279 000005D0 E59F1044 ldr r1, SLit_Spartan_base ; Spartan address 280 000005D4 281 000005D4 E3A000FF mov r0, #&FF ; 282 000005D8 E5C10005 strb r0, [r1, #prog_SB0_ctrl] ; Data 0..7 283 000005DC E5C10009 strb r0, [r1, #prog_VS0_ctrl] ; Data 8..15 284 000005E0 E3A0003B mov r0, #&3B 285 000005E4 E5C10000 strb r0, [r1, #prog_SA0_data] ; Address 0, nWR1, nRD, etc. 286 000005E8 E3A00043 mov r0, #&43 287 000005EC E5C10001 strb r0, [r1, #prog_SA0_ctrl] ; Address 0, nWR1, nRD, etc. 288 000005F0 289 000005F0 E3A00000 mov r0, #&00 290 000005F4 E5C10006 strb r0, [r1, #prog_SB1_data] ; Address 1..8 291 000005F8 E5C10007 strb r0, [r1, #prog_SB1_ctrl] ; 292 000005FC E5C1000A strb r0, [r1, #prog_VS1_data] ; Address 9..16 293 00000600 E5C1000B strb r0, [r1, #prog_VS1_ctrl] ; 294 00000604 E3A00007 mov r0, #&07 ; 295 00000608 E5C10002 strb r0, [r1, #prog_SA1_data] ; Address 17:21, nCS, nReset 296 0000060C E3A00004 mov r0, #&04 ; 297 00000610 E5C10003 strb r0, [r1, #prog_SA1_ctrl] 298 00000614 299 00000614 E8BD0003 ldmfd sp!, {r0, r1} ; 300 00000618 E1A0F00E mov pc, lr ; 301 0000061C 302 0000061C ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 303 0000061C 304 0000061C 40000000 SLit_Spartan_base DCD SPARTAN_base 305 00000620 FFFF0000 SLit_PIO_base DCD PIO_base 306 00000624 307 00000624 ;------------------------------------------------------- ----------------------- 308 00000624 309 00000624 END