ARM Macro Assembler Page 1 1 00000000 ; AT91 boot_table template 2 00000000 ; [JNZ] Modified 20-Mar-2003 3 00000000 4 00000000 GET header.s ; Register definitions etc. 1 00000000 ;------------------------------------------------------- ----------------------- 2 00000000 ; Headers and definitions for AT91 basic set up. 3 00000000 ; Last modified 10/1/03 4 00000000 5 00000000 ; General ARM headers 6 00000000 7 00000000 D SP RN R13 ; Register synonyms 8 00000000 E LR RN R14 9 00000000 F PC RN R15 10 00000000 11 00000000 8 H0 RN R8 ; Thumb register synonyms 12 00000000 9 H1 RN R9 13 00000000 A H2 RN R10 14 00000000 B H3 RN R11 15 00000000 C H4 RN R12 16 00000000 D H5 RN R13 17 00000000 E H6 RN R14 18 00000000 F H7 RN R15 19 00000000 20 00000000 00000080 I_bit EQU &00000080 ; Interrupt disable bit in s tatus word 21 00000000 00000040 F_bit EQU &00000040 ; FIQ disable bit in status word 22 00000000 00000020 T_bit EQU &00000020 ; Thumb bit mask in status w ord 23 00000000 24 00000000 FFFFFFFF TRUE EQU -1 25 00000000 00000000 FALSE EQU 0 26 00000000 27 00000000 0000000F Mode_bits EQU &F ; Bits considered as operati ng mode 28 00000000 00000000 User_mode EQU &0 29 00000000 00000001 FIQ_mode ARM Macro Assembler Page 2 EQU &1 30 00000000 00000002 IRQ_mode EQU &2 31 00000000 00000003 Supervisor_mode EQU &3 32 00000000 00000007 Abort_mode EQU &7 33 00000000 0000000B Undefined_mode EQU &B 34 00000000 0000000F System_mode EQU &F 35 00000000 36 00000000 00000010 mode32 EQU &10 37 00000000 38 00000000 ;------------------------------------------------------- ----------------------- 39 00000000 40 00000000 00000004 cEOT EQU 4 ; Basic ASCII characters 41 00000000 0000000A cLF EQU 10 42 00000000 0000000C cFF EQU 12 43 00000000 0000000D cCR EQU 13 44 00000000 45 00000000 00000000 ttr EQU 0 ; String terminator 46 00000000 47 00000000 FF000000 byte3 EQU &FF000000 ; Byte masks 48 00000000 00FF0000 byte2 EQU &00FF0000 49 00000000 0000FF00 byte1 EQU &0000FF00 50 00000000 000000FF byte0 EQU &000000FF 51 00000000 52 00000000 ;------------------------------------------------------- ----------------------- 53 00000000 ; Specific header for AT91 board 54 00000000 55 00000000 00000000 FASTRAM_base EQU &00000000 ; Prescribed - run time addr ess 56 00000000 57 00000000 00080000 RAM_chip_size EQU &00080000 ; 512 Kbytes 58 00000000 59 00000000 08000000 ROM_base ARM Macro Assembler Page 3 EQU &08000000 ; These are chosen by the us er 60 00000000 10000000 RAM_base EQU &10000000 61 00000000 20000000 VIRTEX_base EQU &20000000 62 00000000 30000000 ETHERNET_base EQU &30000000 63 00000000 40000000 SPARTAN_base EQU &40000000 64 00000000 65 00000000 66 00000000 ; Flags passed to application 67 00000000 00000001 LCD_present_flag EQU &00000001 ; If LCD detected 68 00000000 00000100 Power_up_flag EQU &00000100 ; If power-up reset 69 00000000 00000200 Watchdogged_flag EQU &00000200 ; If watchdog reset 70 00000000 71 00000000 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 72 00000000 73 00000000 00003FFC Serial_number_addr EQU &3FFC ; 74 00000000 75 00000000 00004000 boot_table_address EQU &4000 ; 16Kbytes up to clear botto m block 76 00000000 ; Boot programme MUST be shorter 77 00000000 00000008 boot_table_shifts EQU 8 ; Log of boot table length ( &100) 78 00000000 00000100 boot_table_entry_length EQU 1 :SHL: boot_table_shifts 79 00000000 ; Can't define this the other way :-( 80 00000000 81 00000000 ; Boot block offsets (don't really belong here) 82 00000000 83 00000000 00000004 Btab_flags EQU &04 84 00000000 00000008 Btab_RAM_start EQU &08 85 00000000 0000000C Btab_RAM_length EQU &0C ARM Macro Assembler Page 4 86 00000000 00000010 Btab_ROM_start EQU &10 87 00000000 00000014 Btab_ROM_length EQU &14 88 00000000 00000018 Btab_exec_offset EQU &18 89 00000000 0000001C Btab_exec_CPSR EQU &1C 90 00000000 00000020 Btab_spartan_data EQU &20 91 00000000 00000024 Btab_spartan_length EQU &24 92 00000000 00000028 Btab_virtex_data EQU &28 93 00000000 0000002C Btab_virtex_length EQU &2C 94 00000000 00000030 Btab_LCD_message EQU &30 95 00000000 96 00000000 ; Boot flag definitions 97 00000000 00000001 BtFlg_LCD_message EQU &00000001 98 00000000 00000002 BtFlg_LCD_light EQU &00000002 99 00000000 00000004 BtFlg_LED_on EQU &00000004 100 00000000 00000008 BtFlg_RAM_boot EQU &00000008 ; TBC 101 00000000 00000010 BtFlg_ROM_check EQU &00000010 102 00000000 00000100 BtFlg_RAM_clr_int EQU &00000100 103 00000000 00000200 BtFlg_RAM_clr_ext EQU &00000200 104 00000000 105 00000000 ; FPGA block offsets (don't really belong here either) 106 00000000 107 00000000 00000004 FPGA_offset EQU 4 108 00000000 00000008 FPGA_length EQU 8 ARM Macro Assembler Page 5 109 00000000 110 00000000 111 00000000 ; Default stack sizes (user gets remainder) 112 00000000 113 00000000 00000200 Supervisor_stack EQU &200 114 00000000 00000080 FIQ_stack EQU &80 115 00000000 00000080 IRQ_stack EQU &80 116 00000000 00000080 Abort_stack EQU &80 117 00000000 00000080 Undefined_stack EQU &80 118 00000000 119 00000000 ;------------------------------------------------------- ----------------------- 120 00000000 ; AT91 on-board register definitions 121 00000000 122 00000000 FFFFFFFF DEV_TERMINATE EQU -1 ; Not a peripheral address 123 00000000 ; used to terminate set-up tables 124 00000000 125 00000000 126 00000000 ; External bus interface register addresses 127 00000000 128 00000000 FFE00000 EBI_base EQU &FFE00000 129 00000000 130 00000000 00000000 EBI_CSR0 EQU &00 131 00000000 00000004 EBI_CSR1 EQU &04 132 00000000 00000008 EBI_CSR2 EQU &08 133 00000000 0000000C EBI_CSR3 EQU &0C 134 00000000 00000010 EBI_CSR4 EQU &10 135 00000000 00000014 EBI_CSR5 EQU &14 136 00000000 00000018 EBI_CSR6 EQU &18 137 00000000 0000001C EBI_CSR7 ARM Macro Assembler Page 6 EQU &1C 138 00000000 00000020 EBI_RCR EQU &20 139 00000000 00000024 EBI_MCR EQU &24 140 00000000 141 00000000 ; EBI CSR bit fields 142 00000000 00002000 CSEN EQU &00002000 ; Chip select enable 143 00000000 00001000 BAT EQU &00001000 ; Byte access type (byte sel ect) 144 00000000 00000200 TDF1 EQU &00000200 ; One data float cycle 145 00000000 00000400 TDF2 EQU &00000400 ; Two data float cycles 146 00000000 00000600 TDF3 EQU &00000600 ; Three data float cycles 147 00000000 00000800 TDF4 EQU &00000800 ; Four data float cycles 148 00000000 00000A00 TDF5 EQU &00000A00 ; Five data float cycles 149 00000000 00000C00 TDF6 EQU &00000C00 ; Six data float cycles 150 00000000 00000E00 TDF7 EQU &00000E00 ; Seven data float cycles 151 00000000 00000000 Pg1M EQU &00000000 ; 1 Mbyte pages 152 00000000 00000080 Pg4M EQU &00000080 ; 4 Mbyte pages 153 00000000 00000100 Pg16M EQU &00000100 ; 16 Mbyte pages 154 00000000 00000180 Pg64M EQU &00000180 ; 64 Mbyte pages 155 00000000 00000020 NWS1 EQU &00000020 ; 1 wait state (WSE included ) 156 00000000 00000024 NWS2 EQU &00000024 ; 2 wait states 157 00000000 00000028 NWS3 EQU &00000028 ; 3 wait states 158 00000000 0000002C NWS4 EQU &0000002C ; 4 wait states 159 00000000 00000030 NWS5 EQU &00000030 ; 5 wait states 160 00000000 00000034 NWS6 EQU &00000034 ; 6 wait states 161 00000000 00000038 NWS7 EQU &00000038 ; 7 wait states 162 00000000 0000003C NWS8 EQU &0000003C ; 8 wait states 163 00000000 00000002 DBW8 EQU &00000002 ; 8-bit bus 164 00000000 00000001 DBW16 EQU &00000001 ; 16-bit bus 165 00000000 166 00000000 ; "Special function" register addresses 167 00000000 168 00000000 FFF00000 ARM Macro Assembler Page 7 SF_base EQU &FFF00000 169 00000000 170 00000000 00000000 SF_CIDR EQU &00 171 00000000 00000004 SF_EXID EQU &04 172 00000000 00000008 SF_RSR EQU &08 173 00000000 0000000C SF_MMR EQU &0C 174 00000000 00000018 SF_PMR EQU &18 175 00000000 176 00000000 177 00000000 ; PIO register addresses 178 00000000 179 00000000 FFFF0000 PIO_base EQU &FFFF0000 180 00000000 181 00000000 00000000 PIO_PER EQU &00 182 00000000 00000004 PIO_PDR EQU &04 183 00000000 00000008 PIO_PSR EQU &08 184 00000000 00000010 PIO_OER EQU &10 185 00000000 00000014 PIO_ODR EQU &14 186 00000000 00000018 PIO_OSR EQU &18 187 00000000 00000020 PIO_IFER EQU &20 188 00000000 00000024 PIO_IFDR EQU &24 189 00000000 00000028 PIO_IFSR EQU &28 190 00000000 00000030 PIO_SODR EQU &30 191 00000000 00000034 PIO_CODR EQU &34 192 00000000 00000038 PIO_ODSR EQU &38 193 00000000 0000003C PIO_PDSR EQU &3C 194 00000000 00000040 PIO_IER EQU &40 195 00000000 00000044 PIO_IDR EQU &44 196 00000000 00000048 PIO_IMR EQU &48 ARM Macro Assembler Page 8 197 00000000 0000004C PIO_ISR EQU &4C 198 00000000 199 00000000 200 00000000 ; Power saving register addresses 201 00000000 202 00000000 FFFF4000 PS_base EQU &FFFF4000 203 00000000 204 00000000 00000000 PS_CR EQU &00 205 00000000 00000004 PS_PCER EQU &04 206 00000000 00000008 PS_PCDR EQU &08 207 00000000 0000000C PS_PCSR EQU &0C 208 00000000 209 00000000 210 00000000 ; Watchdog register addresses 211 00000000 212 00000000 FFFF8000 WD_base EQU &FFFF8000 213 00000000 214 00000000 00000000 WD_OMR EQU &00 215 00000000 00000004 WD_CMR EQU &04 216 00000000 00000008 WD_CR EQU &08 217 00000000 0000000C WD_SR EQU &0C 218 00000000 219 00000000 220 00000000 ; USART[0:1] register addresses 221 00000000 222 00000000 FFFD0000 US0_base EQU &FFFD0000 ; Serial port 0 223 00000000 FFFCC000 US1_base EQU &FFFCC000 ; Serial port 1 224 00000000 225 00000000 00000000 US_CR EQU &00 226 00000000 00000004 US_MR EQU &04 227 00000000 00000008 US_IER EQU &08 228 00000000 0000000C US_IDR EQU &0C 229 00000000 00000010 US_IMR EQU &10 230 00000000 00000014 US_CSR EQU &14 231 00000000 00000018 US_RHR EQU &18 232 00000000 0000001C US_THR EQU &1C ARM Macro Assembler Page 9 233 00000000 00000020 US_BRGR EQU &20 234 00000000 00000024 US_RTOR EQU &24 235 00000000 00000028 US_TTGR EQU &28 236 00000000 00000030 US_RPR EQU &30 237 00000000 00000034 US_RCR EQU &34 238 00000000 00000038 US_TPR EQU &38 239 00000000 0000003C US_TCR EQU &3C 240 00000000 241 00000000 ; USART bit definitions 242 00000000 243 00000000 00000001 RxRdy EQU &001 ; Channel Status Register bi ts 244 00000000 00000002 TxRdy EQU &002 245 00000000 00000004 RxBrk EQU &004 246 00000000 00000008 EndRx EQU &008 247 00000000 00000010 EndTx EQU &010 248 00000000 00000020 OvrE EQU &020 249 00000000 00000040 FramE EQU &040 250 00000000 00000080 ParE EQU &080 251 00000000 00000100 Timeout EQU &100 252 00000000 00000200 TxEmpty EQU &200 253 00000000 254 00000000 255 00000000 ; Timer/Counter register addresses 256 00000000 257 00000000 FFFE0000 TC_base EQU &FFFE0000 258 00000000 259 00000000 00000000 TC_CHL0 EQU &00 ; Base offset for TC0 260 00000000 00000040 TC_CHL1 EQU &40 ; Base offset for TC1 261 00000000 00000080 TC_CHL2 EQU &80 ; Base offset for TC2 262 00000000 000000C0 TC_BCR EQU &C0 ; Block control register 263 00000000 000000C4 TC_BMR EQU &C4 ; Block mode register 264 00000000 265 00000000 ; Register offsets within for TC 266 00000000 00000000 TC_CCR EQU &00 ARM Macro Assembler Page 10 267 00000000 00000004 TC_CMR EQU &04 268 00000000 00000010 TC_CVR EQU &10 269 00000000 00000014 TC_RA EQU &14 270 00000000 00000018 TC_RB EQU &18 271 00000000 0000001C TC_RC EQU &1C 272 00000000 00000020 TC_SR EQU &20 273 00000000 00000024 TC_IER EQU &24 274 00000000 00000028 TC_IDR EQU &28 275 00000000 0000002C TC_IMR EQU &2C 276 00000000 277 00000000 278 00000000 ; Interrupt controller register addresses 279 00000000 280 00000000 FFFFF000 AIC_base EQU &FFFFF000 281 00000000 282 00000000 00000000 AIC_SMR0 EQU &00 ; Source mode/priority - FIQ 283 00000000 00000004 AIC_SMR1 EQU &04 ; Source mode/priority - Sof tware 284 00000000 00000008 AIC_SMR2 EQU &08 ; Source mode/priority - USA RT #0 285 00000000 0000000C AIC_SMR3 EQU &0C ; Source mode/priority - USA RT #1 286 00000000 00000010 AIC_SMR4 EQU &10 ; Source mode/priority - Tim er #0 287 00000000 00000014 AIC_SMR5 EQU &14 ; Source mode/priority - Tim er #1 288 00000000 00000018 AIC_SMR6 EQU &18 ; Source mode/priority - Tim er #2 289 00000000 0000001C AIC_SMR7 EQU &1C ; Source mode/priority - Wat chdog 290 00000000 00000020 ARM Macro Assembler Page 11 AIC_SMR8 EQU &20 ; Source mode/priority - PIO 291 00000000 00000040 AIC_SMR16 EQU &40 ; Source mode/priority - IRQ #0 (Spartan) 292 00000000 00000044 AIC_SMR17 EQU &44 ; Source mode/priority - IRQ #1 (Virtex) 293 00000000 00000048 AIC_SMR18 EQU &48 ; Source mode/priority - IRQ #2 (Ethernet) 294 00000000 295 00000000 00000080 AIC_SVR0 EQU &80 ; Source vector - FIQ 296 00000000 00000084 AIC_SVR1 EQU &84 ; Source vector - Software 297 00000000 00000088 AIC_SVR2 EQU &88 ; Source vector - USART #0 298 00000000 0000008C AIC_SVR3 EQU &8C ; Source vector - USART #1 299 00000000 00000090 AIC_SVR4 EQU &90 ; Source vector - Timer #0 300 00000000 00000094 AIC_SVR5 EQU &94 ; Source vector - Timer #1 301 00000000 00000098 AIC_SVR6 EQU &98 ; Source vector - Timer #2 302 00000000 0000009C AIC_SVR7 EQU &9C ; Source vector - Watchdog 303 00000000 000000A0 AIC_SVR8 EQU &A0 ; Source vector - PIO 304 00000000 000000C0 AIC_SVR16 EQU &C0 ; Source vector - IRQ #0 (Sp artan) 305 00000000 000000C4 AIC_SVR17 EQU &C4 ; Source vector - IRQ #1 (Vi rtex) 306 00000000 000000C8 AIC_SVR18 EQU &C8 ; Source vector - IRQ #2 (Et hernet) 307 00000000 308 00000000 00000100 AIC_IVR EQU &100 ; Vector register (IRQ) 309 00000000 00000104 ARM Macro Assembler Page 12 AIC_FVR EQU &104 ; Vector register (FIQ) 310 00000000 00000108 AIC_ISR EQU &108 ; Interrupt status 311 00000000 0000010C AIC_IPR EQU &10C ; (Potential) interrupts pen ding 312 00000000 00000110 AIC_IMR EQU &110 ; Interrupt mask 313 00000000 00000114 AIC_CISR EQU &114 ; Core IRQ/FIQ status 314 00000000 00000120 AIC_IECR EQU &120 ; Interrupt enable 315 00000000 00000124 AIC_IDCR EQU &124 ; Interrupt disable 316 00000000 00000128 AIC_ICCR EQU &128 ; Interrupt clear 317 00000000 0000012C AIC_ISCR EQU &12C ; Interrupt set 318 00000000 00000130 AIC_EOICR EQU &130 ; Signal end of interrupt 319 00000000 00000134 AIC_SPU EQU &134 ; Spurious interrupt vector 320 00000000 321 00000000 ;------------------------------------------------------- ----------------------- 322 00000000 ; `Magic' numbers used to derive baud rate divider from clock speed 323 00000000 324 00000000 0001D7DC baud115k2 EQU &0001D7DC ; 0.1152 * &10000 * 16 325 00000000 00009D49 baud38k4 EQU &00009D49 ; 0.0384 * &10000 * 16 326 00000000 00004EA5 baud19k2 EQU &00004EA5 ; 0.0192 * &10000 * 16 327 00000000 00002752 baud9600 EQU &00002752 ; 0.0096 * &10000 * 16 328 00000000 329 00000000 ;------------------------------------------------------- ----------------------- 330 00000000 ; Local PIO bit definitions for AT91 board 331 00000000 332 00000000 00000200 AT91_Spartan_IRQ EQU &00000200 ; 333 00000000 00000400 AT91_Virtex_IRQ EQU &00000400 ; 334 00000000 00000800 AT91_Ether_IRQ ARM Macro Assembler Page 13 EQU &00000800 ; 335 00000000 00001000 AT91_FIQ EQU &00001000 ; Open drain (Also HDC signa l) 336 00000000 337 00000000 00010000 AT91_Spartan_prog EQU &00010000 ; Active low 338 00000000 00020000 AT91_Virtex_prog EQU &00020000 ; Active low 339 00000000 00040000 AT91_Spartan_init EQU &00040000 ; Active low input 340 00000000 00080000 AT91_Virtex_init EQU &00080000 ; Active low input 341 00000000 342 00000000 00800000 AT91_Spartan_CS1 EQU &00800000 ; Also LCD_RS 343 00000000 00001000 AT91_Spartan_HDC EQU &00001000 ; Also FIQ signal 344 00000000 00002000 AT91_FPGA_baud EQU &00002000 ; Also DOUT - 345 00000000 ; driven low by Spartan at configuration time 346 00000000 347 00000000 00100000 AT91_LCD_light EQU &00100000 ; 348 00000000 349 00000000 00800000 AT91_LCD_RS EQU &00800000 ; Also Spartan CS1 350 00000000 01000000 AT91_LCD_En EQU &01000000 ; 351 00000000 02000000 AT91_LCD_RW EQU &02000000 ; 352 00000000 353 00000000 40000000 AT91_LED_En EQU &40000000 ; 354 00000000 355 00000000 00000080 AT91_LCD_busy EQU &00000080 ; MSB of data bus 356 00000000 357 00000000 ;------------------------------------------------------- ----------------------- 358 00000000 359 00000000 00000000 prog_SA0_data EQU &0 ; XPIO register offsets 360 00000000 00000001 ARM Macro Assembler Page 14 prog_SA0_ctrl EQU &1 361 00000000 00000002 prog_SA1_data EQU &2 362 00000000 00000003 prog_SA1_ctrl EQU &3 363 00000000 00000004 prog_SB0_data EQU &4 364 00000000 00000005 prog_SB0_ctrl EQU &5 365 00000000 00000006 prog_SB1_data EQU &6 366 00000000 00000007 prog_SB1_ctrl EQU &7 367 00000000 00000008 prog_VS0_data EQU &8 368 00000000 00000009 prog_VS0_ctrl EQU &9 369 00000000 0000000A prog_VS1_data EQU &A 370 00000000 0000000B prog_VS1_ctrl EQU &B 371 00000000 372 00000000 ;------------------------------------------------------- ----------------------- 373 00000000 END 5 00000000 6 00000000 GET link_addresses.s ; Addresses (etc.) of p rogrammes 1 00000000 ;------------------------------------------------------- ----------------------- 2 00000000 ; Hand-built table for linking programmes in AT91 boot_t able 3 00000000 ; Last modified 20/11/01 4 00000000 5 00000000 ; Items marked with ** are hand-linked and will need che cking if code expands 6 00000000 7 00000000 8 00000000 00000000 Start EQU 0 9 00000000 10 00000000 00001000 ROM_loader_image_position EQU &1000 ; ** Plenty of space above b oot code 11 00000000 00000500 ROM_loader_image_length EQU &500 ; ** Overestimate ARM Macro Assembler Page 15 12 00000000 00000010 ROM_loader_branch_space EQU &10 ; I wish "ORIGIN" worked :-( 13 00000000 14 00000000 00010000 Mon_ROM EQU &10000 ; ** 15 00000000 00001000 Mon_RAM_image_position EQU &1000 ; ** 16 00000000 00000280 Mon_RAM_image_length EQU &280 ; ** 17 00000000 18 00000000 00020000 Flash_prog EQU &20000 ; ** 19 00000000 00030000 Angel_start EQU &30000 ; ** 20 00000000 21 00000000 00008000 XPIO_config EQU &8000 ; ** 22 00000000 23 00000000 ;------------------------------------------------------- ----------------------- 24 00000000 END 7 00000000 8 00000000 00001000 ROM_loader_image_start EQU ROM_loader_image_position 9 00000000 00001500 ROM_loader_image_end EQU ROM_loader_image_start + ROM_loader_imag e_length 10 00000000 00000FF0 ROM_loader_ROM EQU ROM_loader_image_position - ROM_loader_b ranch_space 11 00000000 00011000 Mon_RAM_start EQU Mon_ROM + Mon_RAM_image_position 12 00000000 00011280 Mon_RAM_end EQU Mon_RAM_start + Mon_RAM_image_length 13 00000000 14 00000000 15 00000000 AREA Boot_table, CODE, READONLY 16 00000000 17 00000000 43 4F 44 45 boot_table DCB "CODE" ; Identifier 18 00000004 00000003 DCD BtFlg_LCD_message :OR: BtFlg_LCD_light 19 00000008 00001000 DCD ROM_loader_image_start - Start ; RAM start 20 0000000C 00000500 DCD ROM_loader_image_end - ROM_loader_image_ start 21 00000010 ; and length ARM Macro Assembler Page 16 22 00000010 00000000 DCD Start ; ROM start 23 00000014 00001400 DCD &1400 ; and length 24 00000018 00000FF0 DCD ROM_loader_ROM - Start ; Start offset 25 0000001C 000000D3 DCD &000000D3 ; and CPSR 26 00000020 00000000 00000000 DCD 0, 0 ; Spartan config. & length 27 00000028 00000000 00000000 DCD 0, 0 ; Virtex config. & length 28 00000030 0C 4F 6E 2D 62 6F 61 72 64 20 46 6C 61 73 68 0A DCB cFF, "On-board Flash", cLF 29 00000040 52 4F 4D 20 4C 6F 61 64 65 72 00 DCB "ROM Loader", ttr 30 0000004B 31 0000004B ; DCB cFF,"Flash ROM loader", ttr 32 0000004B ; DCB "**************" ; LCD second line 33 0000004B ; DCB "On-board flash l" ; User's text 34 0000004B ; DCB "oader, etc. " ; 35 0000004B 36 0000004B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ARM Macro Assembler Page 17 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ALIGN boot_table_entry_length 37 00000100 38 00000100 43 4F 44 45 DCB "CODE" ; Identifier 39 00000104 00000005 DCD BtFlg_LCD_message :OR: BtFlg_LED_on 40 00000108 00011000 DCD Mon_RAM_start - Start ; RAM start 41 0000010C 00000280 DCD Mon_RAM_end - Mon_RAM_start ; and length 42 00000110 00010000 00002800 DCD Mon_ROM, &2800 ; ROM start and length 43 00000118 00000000 000000D3 DCD &00000000, &000000D3 ; Start offset and CPSR 44 00000120 00008000 DCD XPIO_config - Start ; Spartan config. ROM offset 45 00000124 00004000 DCD &4000 ; Spartan length 46 00000128 00000000 00000000 DCD 0, 0 ; Virtex config. & length 47 00000130 0C 20 20 20 4B 6F 6D 6F 64 6F 20 41 52 4D 20 20 20 0A DCB cFF, " Komodo ARM ", cLF 48 00000142 45 6E 76 69 72 6F 6E 6D 65 6E 74 20 76 32 2E 30 00 DCB "Environment v2.0", ttr 49 00000153 50 00000153 ; DCB cFF, 0 ; Just clear screen 51 00000153 ; DCB "Komodo back end " ; User's text ARM Macro Assembler Page 18 52 00000153 53 00000153 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ALIGN boot_table_entry_length ARM Macro Assembler Page 19 54 00000200 55 00000200 43 4F 44 45 DCB "CODE" ; Identifier 56 00000204 00000007 DCD BtFlg_LCD_message :OR: BtFlg_LCD_light : OR: BtFlg_LED_on 57 00000208 00000000 00000000 DCD 0, 0 ; RAM start and length 58 00000210 00020000 00000700 DCD Flash_prog, &700 ; ROM start and length 59 00000218 00000000 000000D3 DCD &00000000, &000000D3 ; Start offset and CPSR 60 00000220 00008000 DCD XPIO_config - Start ; Spartan config. ROM offset 61 00000224 00004000 DCD &4000 ; Spartan length 62 00000228 00000000 00000000 DCD 0, 0 ; Virtex config. & length 63 00000230 0C 48 2F 57 2D 62 61 73 65 64 20 46 6C 61 73 68 0A DCB cFF, "H/W-based Flash", cLF 64 00000241 50 72 6F 67 72 61 6D 6D 65 72 2F 54 65 73 74 00 DCB "Programmer/Test", ttr 65 00000251 ; DCB cFF,"Remote flash",cLF,"loader", ttr 66 00000251 ; DCB "Spartan test & r" ; User's text 67 00000251 ; DCB "emote flash prog" ; 68 00000251 ; DCB "rammer." ; 69 00000251 70 00000251 71 00000251 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ARM Macro Assembler Page 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ALIGN boot_table_entry_length 72 00000300 73 00000300 43 4F 44 45 DCB "CODE" ; Identifier 74 00000304 00000007 DCD BtFlg_LCD_message :OR: BtFlg_LCD_light : OR: BtFlg_LED_on 75 00000308 00000000 00000000 DCD 0, 0 ; RAM start and length 76 00000310 00030000 00010000 DCD Angel_start, &10000 ; ROM start and length 77 00000318 00000000 000000D3 DCD &00000000, &000000D3 ; Start offset and CPSR 78 00000320 00008000 DCD XPIO_config - Start ; Spartan config. ROM offset 79 00000324 00004000 DCD &4000 ; Spartan length 80 00000328 00000000 00000000 DCD 0, 0 ; Virtex config. & length 81 00000330 0C 01 02 20 20 41 6E 67 65 6C 20 31 ARM Macro Assembler Page 21 2E 30 34 0A DCB cFF,1,2," Angel 1.04",cLF 82 00000340 03 04 00 DCB 3,4, ttr ; LCD message 83 00000343 41 6E 67 65 6C 20 31 2E 30 34 20 DCB "Angel 1.04 " ; User's text 84 0000034E 64 6F 77 6E 6C 6F 61 64 65 64 20 66 72 6F 6D 20 77 77 77 2E 61 74 6D 65 6C 2E 63 6F 6D 20 DCB "downloaded from www.atmel.com " 85 0000036C 61 6E 64 20 63 75 73 74 6F 6D 69 73 65 64 20 62 79 20 53 74 65 76 65 20 54 65 6D 70 6C 65 20 DCB "and customised by Steve Temple " 86 0000038B 31 39 74 68 20 46 65 62 72 75 61 72 79 20 32 30 30 32 DCB "19th February 2002" ; 87 0000039D 88 0000039D 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ARM Macro Assembler Page 22 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ALIGN boot_table_entry_length 89 00000400 90 00000400 91 00000400 ;------------------------------------------------------- ----------------------- 92 00000400 93 00000400 END