ARM Macro Assembler Page 1 1 00000000 ; AT91 board bootstrap and dispatch code 2 00000000 ; [JNZ] Modified 20-Mar-2003 3 00000000 4 00000000 ; Should review all timing setups for production - prob. okay 5 00000000 ; 6 00000000 ; Add self-test and various diagnostics 7 00000000 ; 8 00000000 ; Write verification in Flash programmer 9 00000000 ; Flash programmer should initially listen to both seria l ports 10 00000000 ; 11 00000000 ; Both serial ports initialised to 19.2kbaud 12 00000000 ; 13 00000000 14 00000000 00000001 Maker EQU 1 15 00000000 00000002 Version EQU 2 16 00000000 00000009 day EQU 9 17 00000000 00000001 month EQU 1 18 00000000 00000003 year EQU 03 19 00000000 20 00000000 ; [JNZ] Use a 32MHz clock, not 24MHz 21 00000000 00000020 MHz EQU 32 22 00000000 ;MHz EQU 24 23 00000000 00200000 clock_rate EQU &10000 * MHz ; 16.16 bit fixed point num ber (MHz) 24 00000000 25 00000000 26 00000000 GET header.s ; Register definitions etc. 1 00000000 ;------------------------------------------------------- ----------------------- 2 00000000 ; Headers and definitions for AT91 basic set up. 3 00000000 ; Last modified 10/1/03 4 00000000 5 00000000 ; General ARM headers 6 00000000 7 00000000 D SP RN R13 ; Register synonyms 8 00000000 E LR RN R14 9 00000000 F PC RN R15 10 00000000 11 00000000 8 H0 RN R8 ; Thumb register synonyms 12 00000000 9 H1 RN R9 13 00000000 A H2 RN R10 14 00000000 B H3 RN R11 ARM Macro Assembler Page 2 15 00000000 C H4 RN R12 16 00000000 D H5 RN R13 17 00000000 E H6 RN R14 18 00000000 F H7 RN R15 19 00000000 20 00000000 00000080 I_bit EQU &00000080 ; Interrupt disable bit in s tatus word 21 00000000 00000040 F_bit EQU &00000040 ; FIQ disable bit in status word 22 00000000 00000020 T_bit EQU &00000020 ; Thumb bit mask in status w ord 23 00000000 24 00000000 FFFFFFFF TRUE EQU -1 25 00000000 00000000 FALSE EQU 0 26 00000000 27 00000000 0000000F Mode_bits EQU &F ; Bits considered as operati ng mode 28 00000000 00000000 User_mode EQU &0 29 00000000 00000001 FIQ_mode EQU &1 30 00000000 00000002 IRQ_mode EQU &2 31 00000000 00000003 Supervisor_mode EQU &3 32 00000000 00000007 Abort_mode EQU &7 33 00000000 0000000B Undefined_mode EQU &B 34 00000000 0000000F System_mode EQU &F 35 00000000 36 00000000 00000010 mode32 EQU &10 37 00000000 38 00000000 ;------------------------------------------------------- ----------------------- 39 00000000 40 00000000 00000004 cEOT EQU 4 ; Basic ASCII characters 41 00000000 0000000A ARM Macro Assembler Page 3 cLF EQU 10 42 00000000 0000000C cFF EQU 12 43 00000000 0000000D cCR EQU 13 44 00000000 45 00000000 00000000 ttr EQU 0 ; String terminator 46 00000000 47 00000000 FF000000 byte3 EQU &FF000000 ; Byte masks 48 00000000 00FF0000 byte2 EQU &00FF0000 49 00000000 0000FF00 byte1 EQU &0000FF00 50 00000000 000000FF byte0 EQU &000000FF 51 00000000 52 00000000 ;------------------------------------------------------- ----------------------- 53 00000000 ; Specific header for AT91 board 54 00000000 55 00000000 00000000 FASTRAM_base EQU &00000000 ; Prescribed - run time addr ess 56 00000000 57 00000000 00080000 RAM_chip_size EQU &00080000 ; 512 Kbytes 58 00000000 59 00000000 08000000 ROM_base EQU &08000000 ; These are chosen by the us er 60 00000000 10000000 RAM_base EQU &10000000 61 00000000 20000000 VIRTEX_base EQU &20000000 62 00000000 30000000 ETHERNET_base EQU &30000000 63 00000000 40000000 SPARTAN_base EQU &40000000 64 00000000 65 00000000 66 00000000 ; Flags passed to application 67 00000000 00000001 LCD_present_flag EQU &00000001 ; If LCD detected 68 00000000 00000100 Power_up_flag EQU &00000100 ; If power-up reset 69 00000000 00000200 Watchdogged_flag EQU &00000200 ; If watchdog reset ARM Macro Assembler Page 4 70 00000000 71 00000000 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 72 00000000 73 00000000 00003FFC Serial_number_addr EQU &3FFC ; 74 00000000 75 00000000 00004000 boot_table_address EQU &4000 ; 16Kbytes up to clear botto m block 76 00000000 ; Boot programme MUST be shorter 77 00000000 00000008 boot_table_shifts EQU 8 ; Log of boot table length ( &100) 78 00000000 00000100 boot_table_entry_length EQU 1 :SHL: boot_table_shifts 79 00000000 ; Can't define this the other way :-( 80 00000000 81 00000000 ; Boot block offsets (don't really belong here) 82 00000000 83 00000000 00000004 Btab_flags EQU &04 84 00000000 00000008 Btab_RAM_start EQU &08 85 00000000 0000000C Btab_RAM_length EQU &0C 86 00000000 00000010 Btab_ROM_start EQU &10 87 00000000 00000014 Btab_ROM_length EQU &14 88 00000000 00000018 Btab_exec_offset EQU &18 89 00000000 0000001C Btab_exec_CPSR EQU &1C 90 00000000 00000020 Btab_spartan_data EQU &20 91 00000000 00000024 Btab_spartan_length EQU &24 92 00000000 00000028 Btab_virtex_data EQU &28 93 00000000 0000002C Btab_virtex_length EQU &2C 94 00000000 00000030 Btab_LCD_message ARM Macro Assembler Page 5 EQU &30 95 00000000 96 00000000 ; Boot flag definitions 97 00000000 00000001 BtFlg_LCD_message EQU &00000001 98 00000000 00000002 BtFlg_LCD_light EQU &00000002 99 00000000 00000004 BtFlg_LED_on EQU &00000004 100 00000000 00000008 BtFlg_RAM_boot EQU &00000008 ; TBC 101 00000000 00000010 BtFlg_ROM_check EQU &00000010 102 00000000 00000100 BtFlg_RAM_clr_int EQU &00000100 103 00000000 00000200 BtFlg_RAM_clr_ext EQU &00000200 104 00000000 105 00000000 ; FPGA block offsets (don't really belong here either) 106 00000000 107 00000000 00000004 FPGA_offset EQU 4 108 00000000 00000008 FPGA_length EQU 8 109 00000000 110 00000000 111 00000000 ; Default stack sizes (user gets remainder) 112 00000000 113 00000000 00000200 Supervisor_stack EQU &200 114 00000000 00000080 FIQ_stack EQU &80 115 00000000 00000080 IRQ_stack EQU &80 116 00000000 00000080 Abort_stack EQU &80 117 00000000 00000080 Undefined_stack EQU &80 118 00000000 119 00000000 ;------------------------------------------------------- ----------------------- 120 00000000 ; AT91 on-board register definitions 121 00000000 122 00000000 FFFFFFFF DEV_TERMINATE ARM Macro Assembler Page 6 EQU -1 ; Not a peripheral address 123 00000000 ; used to terminate set-up tables 124 00000000 125 00000000 126 00000000 ; External bus interface register addresses 127 00000000 128 00000000 FFE00000 EBI_base EQU &FFE00000 129 00000000 130 00000000 00000000 EBI_CSR0 EQU &00 131 00000000 00000004 EBI_CSR1 EQU &04 132 00000000 00000008 EBI_CSR2 EQU &08 133 00000000 0000000C EBI_CSR3 EQU &0C 134 00000000 00000010 EBI_CSR4 EQU &10 135 00000000 00000014 EBI_CSR5 EQU &14 136 00000000 00000018 EBI_CSR6 EQU &18 137 00000000 0000001C EBI_CSR7 EQU &1C 138 00000000 00000020 EBI_RCR EQU &20 139 00000000 00000024 EBI_MCR EQU &24 140 00000000 141 00000000 ; EBI CSR bit fields 142 00000000 00002000 CSEN EQU &00002000 ; Chip select enable 143 00000000 00001000 BAT EQU &00001000 ; Byte access type (byte sel ect) 144 00000000 00000200 TDF1 EQU &00000200 ; One data float cycle 145 00000000 00000400 TDF2 EQU &00000400 ; Two data float cycles 146 00000000 00000600 TDF3 EQU &00000600 ; Three data float cycles 147 00000000 00000800 TDF4 EQU &00000800 ; Four data float cycles 148 00000000 00000A00 TDF5 EQU &00000A00 ; Five data float cycles 149 00000000 00000C00 TDF6 EQU &00000C00 ; Six data float cycles 150 00000000 00000E00 TDF7 EQU &00000E00 ; Seven data float cycles ARM Macro Assembler Page 7 151 00000000 00000000 Pg1M EQU &00000000 ; 1 Mbyte pages 152 00000000 00000080 Pg4M EQU &00000080 ; 4 Mbyte pages 153 00000000 00000100 Pg16M EQU &00000100 ; 16 Mbyte pages 154 00000000 00000180 Pg64M EQU &00000180 ; 64 Mbyte pages 155 00000000 00000020 NWS1 EQU &00000020 ; 1 wait state (WSE included ) 156 00000000 00000024 NWS2 EQU &00000024 ; 2 wait states 157 00000000 00000028 NWS3 EQU &00000028 ; 3 wait states 158 00000000 0000002C NWS4 EQU &0000002C ; 4 wait states 159 00000000 00000030 NWS5 EQU &00000030 ; 5 wait states 160 00000000 00000034 NWS6 EQU &00000034 ; 6 wait states 161 00000000 00000038 NWS7 EQU &00000038 ; 7 wait states 162 00000000 0000003C NWS8 EQU &0000003C ; 8 wait states 163 00000000 00000002 DBW8 EQU &00000002 ; 8-bit bus 164 00000000 00000001 DBW16 EQU &00000001 ; 16-bit bus 165 00000000 166 00000000 ; "Special function" register addresses 167 00000000 168 00000000 FFF00000 SF_base EQU &FFF00000 169 00000000 170 00000000 00000000 SF_CIDR EQU &00 171 00000000 00000004 SF_EXID EQU &04 172 00000000 00000008 SF_RSR EQU &08 173 00000000 0000000C SF_MMR EQU &0C 174 00000000 00000018 SF_PMR EQU &18 175 00000000 176 00000000 177 00000000 ; PIO register addresses 178 00000000 179 00000000 FFFF0000 PIO_base EQU &FFFF0000 180 00000000 181 00000000 00000000 PIO_PER EQU &00 182 00000000 00000004 PIO_PDR EQU &04 183 00000000 00000008 PIO_PSR EQU &08 ARM Macro Assembler Page 8 184 00000000 00000010 PIO_OER EQU &10 185 00000000 00000014 PIO_ODR EQU &14 186 00000000 00000018 PIO_OSR EQU &18 187 00000000 00000020 PIO_IFER EQU &20 188 00000000 00000024 PIO_IFDR EQU &24 189 00000000 00000028 PIO_IFSR EQU &28 190 00000000 00000030 PIO_SODR EQU &30 191 00000000 00000034 PIO_CODR EQU &34 192 00000000 00000038 PIO_ODSR EQU &38 193 00000000 0000003C PIO_PDSR EQU &3C 194 00000000 00000040 PIO_IER EQU &40 195 00000000 00000044 PIO_IDR EQU &44 196 00000000 00000048 PIO_IMR EQU &48 197 00000000 0000004C PIO_ISR EQU &4C 198 00000000 199 00000000 200 00000000 ; Power saving register addresses 201 00000000 202 00000000 FFFF4000 PS_base EQU &FFFF4000 203 00000000 204 00000000 00000000 PS_CR EQU &00 205 00000000 00000004 PS_PCER EQU &04 206 00000000 00000008 PS_PCDR EQU &08 207 00000000 0000000C PS_PCSR EQU &0C 208 00000000 209 00000000 210 00000000 ; Watchdog register addresses 211 00000000 212 00000000 FFFF8000 WD_base EQU &FFFF8000 213 00000000 214 00000000 00000000 WD_OMR EQU &00 ARM Macro Assembler Page 9 215 00000000 00000004 WD_CMR EQU &04 216 00000000 00000008 WD_CR EQU &08 217 00000000 0000000C WD_SR EQU &0C 218 00000000 219 00000000 220 00000000 ; USART[0:1] register addresses 221 00000000 222 00000000 FFFD0000 US0_base EQU &FFFD0000 ; Serial port 0 223 00000000 FFFCC000 US1_base EQU &FFFCC000 ; Serial port 1 224 00000000 225 00000000 00000000 US_CR EQU &00 226 00000000 00000004 US_MR EQU &04 227 00000000 00000008 US_IER EQU &08 228 00000000 0000000C US_IDR EQU &0C 229 00000000 00000010 US_IMR EQU &10 230 00000000 00000014 US_CSR EQU &14 231 00000000 00000018 US_RHR EQU &18 232 00000000 0000001C US_THR EQU &1C 233 00000000 00000020 US_BRGR EQU &20 234 00000000 00000024 US_RTOR EQU &24 235 00000000 00000028 US_TTGR EQU &28 236 00000000 00000030 US_RPR EQU &30 237 00000000 00000034 US_RCR EQU &34 238 00000000 00000038 US_TPR EQU &38 239 00000000 0000003C US_TCR EQU &3C 240 00000000 241 00000000 ; USART bit definitions 242 00000000 243 00000000 00000001 RxRdy EQU &001 ; Channel Status Register bi ts 244 00000000 00000002 TxRdy EQU &002 245 00000000 00000004 RxBrk EQU &004 246 00000000 00000008 EndRx EQU &008 ARM Macro Assembler Page 10 247 00000000 00000010 EndTx EQU &010 248 00000000 00000020 OvrE EQU &020 249 00000000 00000040 FramE EQU &040 250 00000000 00000080 ParE EQU &080 251 00000000 00000100 Timeout EQU &100 252 00000000 00000200 TxEmpty EQU &200 253 00000000 254 00000000 255 00000000 ; Timer/Counter register addresses 256 00000000 257 00000000 FFFE0000 TC_base EQU &FFFE0000 258 00000000 259 00000000 00000000 TC_CHL0 EQU &00 ; Base offset for TC0 260 00000000 00000040 TC_CHL1 EQU &40 ; Base offset for TC1 261 00000000 00000080 TC_CHL2 EQU &80 ; Base offset for TC2 262 00000000 000000C0 TC_BCR EQU &C0 ; Block control register 263 00000000 000000C4 TC_BMR EQU &C4 ; Block mode register 264 00000000 265 00000000 ; Register offsets within for TC 266 00000000 00000000 TC_CCR EQU &00 267 00000000 00000004 TC_CMR EQU &04 268 00000000 00000010 TC_CVR EQU &10 269 00000000 00000014 TC_RA EQU &14 270 00000000 00000018 TC_RB EQU &18 271 00000000 0000001C TC_RC EQU &1C 272 00000000 00000020 TC_SR EQU &20 273 00000000 00000024 TC_IER EQU &24 274 00000000 00000028 TC_IDR EQU &28 275 00000000 0000002C TC_IMR EQU &2C 276 00000000 277 00000000 278 00000000 ; Interrupt controller register addresses 279 00000000 280 00000000 FFFFF000 AIC_base EQU &FFFFF000 281 00000000 ARM Macro Assembler Page 11 282 00000000 00000000 AIC_SMR0 EQU &00 ; Source mode/priority - FIQ 283 00000000 00000004 AIC_SMR1 EQU &04 ; Source mode/priority - Sof tware 284 00000000 00000008 AIC_SMR2 EQU &08 ; Source mode/priority - USA RT #0 285 00000000 0000000C AIC_SMR3 EQU &0C ; Source mode/priority - USA RT #1 286 00000000 00000010 AIC_SMR4 EQU &10 ; Source mode/priority - Tim er #0 287 00000000 00000014 AIC_SMR5 EQU &14 ; Source mode/priority - Tim er #1 288 00000000 00000018 AIC_SMR6 EQU &18 ; Source mode/priority - Tim er #2 289 00000000 0000001C AIC_SMR7 EQU &1C ; Source mode/priority - Wat chdog 290 00000000 00000020 AIC_SMR8 EQU &20 ; Source mode/priority - PIO 291 00000000 00000040 AIC_SMR16 EQU &40 ; Source mode/priority - IRQ #0 (Spartan) 292 00000000 00000044 AIC_SMR17 EQU &44 ; Source mode/priority - IRQ #1 (Virtex) 293 00000000 00000048 AIC_SMR18 EQU &48 ; Source mode/priority - IRQ #2 (Ethernet) 294 00000000 295 00000000 00000080 AIC_SVR0 EQU &80 ; Source vector - FIQ 296 00000000 00000084 AIC_SVR1 EQU &84 ; Source vector - Software 297 00000000 00000088 AIC_SVR2 EQU &88 ; Source vector - USART #0 298 00000000 0000008C ARM Macro Assembler Page 12 AIC_SVR3 EQU &8C ; Source vector - USART #1 299 00000000 00000090 AIC_SVR4 EQU &90 ; Source vector - Timer #0 300 00000000 00000094 AIC_SVR5 EQU &94 ; Source vector - Timer #1 301 00000000 00000098 AIC_SVR6 EQU &98 ; Source vector - Timer #2 302 00000000 0000009C AIC_SVR7 EQU &9C ; Source vector - Watchdog 303 00000000 000000A0 AIC_SVR8 EQU &A0 ; Source vector - PIO 304 00000000 000000C0 AIC_SVR16 EQU &C0 ; Source vector - IRQ #0 (Sp artan) 305 00000000 000000C4 AIC_SVR17 EQU &C4 ; Source vector - IRQ #1 (Vi rtex) 306 00000000 000000C8 AIC_SVR18 EQU &C8 ; Source vector - IRQ #2 (Et hernet) 307 00000000 308 00000000 00000100 AIC_IVR EQU &100 ; Vector register (IRQ) 309 00000000 00000104 AIC_FVR EQU &104 ; Vector register (FIQ) 310 00000000 00000108 AIC_ISR EQU &108 ; Interrupt status 311 00000000 0000010C AIC_IPR EQU &10C ; (Potential) interrupts pen ding 312 00000000 00000110 AIC_IMR EQU &110 ; Interrupt mask 313 00000000 00000114 AIC_CISR EQU &114 ; Core IRQ/FIQ status 314 00000000 00000120 AIC_IECR EQU &120 ; Interrupt enable 315 00000000 00000124 AIC_IDCR EQU &124 ; Interrupt disable 316 00000000 00000128 AIC_ICCR EQU &128 ; Interrupt clear 317 00000000 0000012C AIC_ISCR EQU &12C ; Interrupt set 318 00000000 00000130 AIC_EOICR EQU &130 ; Signal end of interrupt ARM Macro Assembler Page 13 319 00000000 00000134 AIC_SPU EQU &134 ; Spurious interrupt vector 320 00000000 321 00000000 ;------------------------------------------------------- ----------------------- 322 00000000 ; `Magic' numbers used to derive baud rate divider from clock speed 323 00000000 324 00000000 0001D7DC baud115k2 EQU &0001D7DC ; 0.1152 * &10000 * 16 325 00000000 00009D49 baud38k4 EQU &00009D49 ; 0.0384 * &10000 * 16 326 00000000 00004EA5 baud19k2 EQU &00004EA5 ; 0.0192 * &10000 * 16 327 00000000 00002752 baud9600 EQU &00002752 ; 0.0096 * &10000 * 16 328 00000000 329 00000000 ;------------------------------------------------------- ----------------------- 330 00000000 ; Local PIO bit definitions for AT91 board 331 00000000 332 00000000 00000200 AT91_Spartan_IRQ EQU &00000200 ; 333 00000000 00000400 AT91_Virtex_IRQ EQU &00000400 ; 334 00000000 00000800 AT91_Ether_IRQ EQU &00000800 ; 335 00000000 00001000 AT91_FIQ EQU &00001000 ; Open drain (Also HDC signa l) 336 00000000 337 00000000 00010000 AT91_Spartan_prog EQU &00010000 ; Active low 338 00000000 00020000 AT91_Virtex_prog EQU &00020000 ; Active low 339 00000000 00040000 AT91_Spartan_init EQU &00040000 ; Active low input 340 00000000 00080000 AT91_Virtex_init EQU &00080000 ; Active low input 341 00000000 342 00000000 00800000 AT91_Spartan_CS1 EQU &00800000 ; Also LCD_RS 343 00000000 00001000 AT91_Spartan_HDC EQU &00001000 ; Also FIQ signal 344 00000000 00002000 ARM Macro Assembler Page 14 AT91_FPGA_baud EQU &00002000 ; Also DOUT - 345 00000000 ; driven low by Spartan at configuration time 346 00000000 347 00000000 00100000 AT91_LCD_light EQU &00100000 ; 348 00000000 349 00000000 00800000 AT91_LCD_RS EQU &00800000 ; Also Spartan CS1 350 00000000 01000000 AT91_LCD_En EQU &01000000 ; 351 00000000 02000000 AT91_LCD_RW EQU &02000000 ; 352 00000000 353 00000000 40000000 AT91_LED_En EQU &40000000 ; 354 00000000 355 00000000 00000080 AT91_LCD_busy EQU &00000080 ; MSB of data bus 356 00000000 357 00000000 ;------------------------------------------------------- ----------------------- 358 00000000 359 00000000 00000000 prog_SA0_data EQU &0 ; XPIO register offsets 360 00000000 00000001 prog_SA0_ctrl EQU &1 361 00000000 00000002 prog_SA1_data EQU &2 362 00000000 00000003 prog_SA1_ctrl EQU &3 363 00000000 00000004 prog_SB0_data EQU &4 364 00000000 00000005 prog_SB0_ctrl EQU &5 365 00000000 00000006 prog_SB1_data EQU &6 366 00000000 00000007 prog_SB1_ctrl EQU &7 367 00000000 00000008 prog_VS0_data EQU &8 368 00000000 00000009 prog_VS0_ctrl EQU &9 ARM Macro Assembler Page 15 369 00000000 0000000A prog_VS1_data EQU &A 370 00000000 0000000B prog_VS1_ctrl EQU &B 371 00000000 372 00000000 ;------------------------------------------------------- ----------------------- 373 00000000 END 27 00000000 GET link_addresses.s ; Addresses (etc.) of p rogrammes 1 00000000 ;------------------------------------------------------- ----------------------- 2 00000000 ; Hand-built table for linking programmes in AT91 boot_t able 3 00000000 ; Last modified 20/11/01 4 00000000 5 00000000 ; Items marked with ** are hand-linked and will need che cking if code expands 6 00000000 7 00000000 8 00000000 00000000 Start EQU 0 9 00000000 10 00000000 00001000 ROM_loader_image_position EQU &1000 ; ** Plenty of space above b oot code 11 00000000 00000500 ROM_loader_image_length EQU &500 ; ** Overestimate 12 00000000 00000010 ROM_loader_branch_space EQU &10 ; I wish "ORIGIN" worked :-( 13 00000000 14 00000000 00010000 Mon_ROM EQU &10000 ; ** 15 00000000 00001000 Mon_RAM_image_position EQU &1000 ; ** 16 00000000 00000280 Mon_RAM_image_length EQU &280 ; ** 17 00000000 18 00000000 00020000 Flash_prog EQU &20000 ; ** 19 00000000 00030000 Angel_start EQU &30000 ; ** 20 00000000 21 00000000 00008000 XPIO_config EQU &8000 ; ** 22 00000000 23 00000000 ;------------------------------------------------------- ----------------------- ARM Macro Assembler Page 16 24 00000000 END 28 00000000 29 00000000 00000053 Watchdogged_code EQU &53 ; Chip's record of reset 30 00000000 31 00000000 32 00000000 00020000 No_boot_SW_delay EQU &20000 ; 33 00000000 00000064 LCD_int_SW_delay EQU 100 ; 34 00000000 35 00000000 ;------------------------------------------------------- ----------------------- 36 00000000 37 00000000 ; Cold boot from ROM 38 00000000 39 00000000 AREA boot, CODE, READONLY 40 00000000 ENTRY 41 00000000 42 00000000 ;Start 43 00000000 E59F15AC ldr r1, Lit_PIO_base ; Read DIP switches <7:4> 44 00000004 E591C03C ldr r12, [r1,#PIO_PDSR] ; & power-up state <0> 45 00000008 46 00000008 E28FE07C adr lr, Start1 ; `Return' address 47 0000000C EA0000F9 b Device_init ; Initialise on-chip I/O 48 00000010 49 00000010 41 54 39 31 20 42 6F 6F 74 20 63 6F 64 65 20 76 65 72 73 69 6F 6E 20 30 2E 32 20 DCB "AT91 Boot code version 0.2 " 50 0000002B 4A 2E 20 47 61 72 73 69 64 65 2C 20 28 63 29 20 55 6E 69 76 65 72 73 69 74 79 20 6F 66 20 4D 61 6E 63 68 65 73 74 65 72 20 DCB "J. Garside, (c) University of Mancheste r " 51 00000054 4A 61 6E 75 61 72 79 20 32 30 30 33 DCB "January 2003" ARM Macro Assembler Page 17 52 00000060 53 00000060 ALIGN 54 00000060 55 00000060 ; Pack version & date into 32 bits 56 00000060 01024883 Version_ID DCD Maker*&1000000 + Version*&10000 + day*&8 00 + month*&80 + year 57 00000064 58 00000064 04040000 00001000 CIDR_table DCD &04040000, &00001000 ; 40400, 4K 59 0000006C 04080000 00002000 DCD &04080000, &00002000 ; 40800, 8K 60 00000074 04080700 00002000 DCD &04080700, &00002000 ; 40807, 8K 61 0000007C 04000800 00040000 DCD &04000800, &00040000 ; 40008, 256K 62 00000084 00000000 00000100 DCD &00000000, &00000100 ; Unknown, 256bytes - for now @@@ 63 0000008C 64 0000008C E59F1524 Start1 ldr r1, Lit_EBI_base ; 65 00000090 E3A00001 mov r0, #1 ; 66 00000094 E5810020 str r0, [r1, #EBI_RCR] ; Remap memory 67 00000098 E28FF302 add pc, pc, #ROM_base ; This instruction will be 68 0000009C ; in the prefetch buffer 69 0000009C E1A00000 nop ; Jump will also add 8 70 000000A0 E1A00000 nop ; So pad 71 000000A4 72 000000A4 ; The on-chip RAM is now at address 00000000 and we are running in the ROM 73 000000A4 ; starting at ROM_base. 74 000000A4 ; R12<7:4> holds the boot DIP switch reading; <0> holds the power-up bit 75 000000A4 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 76 000000A4 ; On-chip RAM size can be interpreted from chip ID 77 000000A4 78 000000A4 E59FD510 ldr r13, Lit_SF_base ; Sort out a stack at the 79 000000A8 E59DD000 ldr r13, [r13, #SF_CIDR] ; top of the internal RAM 80 000000AC 81 000000AC E3CDD0FF bic r13, r13, #&000000FF ; Lose version et alia 82 000000B0 E3CDD20F bic r13, r13, #&F0000000 ; 83 000000B4 E24F8058 adr r8, CIDR_table ; 84 000000B8 85 000000B8 E4984008 CIDR_loop ldr r4, [r8], #8 ; Read tag and move to next 86 000000BC E3540000 cmp r4, #0 ; Zero is CIDR table termina tor 87 000000C0 0A000001 beq CIDR_loop_out ; 88 000000C4 ARM Macro Assembler Page 18 89 000000C4 E154000D cmp r4, r13 ; Check our ID 90 000000C8 1AFFFFFA bne CIDR_loop ; no - not this one 91 000000CC 92 000000CC E518D004 CIDR_loop_out ldr sp, [r8, #-4] ; Back to last data field 93 000000D0 ; So default supervisor stack 94 000000D0 95 000000D0 ; @@@ If device not recognised we should do something sp ecial 96 000000D0 97 000000D0 ; Supervisor stack pointer now set up 98 000000D0 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 99 000000D0 ; See how much RAM we have on the current board 100 000000D0 ; This assumes that and all RAM chips are 512KB 101 000000D0 102 000000D0 E3A08201 mov r8, #RAM_base ; Count the amount of RAM 103 000000D4 E59F44F4 ldr r4, Lit_RAM_test_val ; 104 000000D8 E1E05004 mvn r5, r4 ; Inverse value 105 000000DC 106 000000DC E3A03008 mov r3, #8 ; Maximum number of chips 107 000000E0 108 000000E0 E89800C0 RAM_tally_loop ldmia r8, {r6, r7} ; Read old values 109 000000E4 E8880030 stmia r8, {r4, r5} ; Try new values 110 000000E8 ; (Scramble bus if floating) 111 000000E8 E5980000 ldr r0, [r8] ; 112 000000EC E1500004 cmp r0, r4 ; Loads stored value? 113 000000F0 1A00000F bne RAM_tally_done ; No! 114 000000F4 E88800C0 stmia r8, {r6, r7} ; Restore original contents 115 000000F8 E2888702 add r8, r8, #RAM_chip_size ; Move to next chip 116 000000FC 117 000000FC E2533001 subs r3, r3, #1 ; 118 00000100 8AFFFFF6 bhi RAM_tally_loop ; 119 00000104 ; Fall out if RAM address -space- completely occupied 120 00000104 121 00000104 E3A04201 mov r4, #RAM_base ; Check for aliasing 122 00000108 E2845702 add r5, r4, #RAM_chip_size ; Move up to second(?) chip 123 0000010C E5946000 ldr r6, [r4] ; Read value from RAM #0 124 00000110 E5957000 ldr r7, [r5] ; Read value from RAM #1 (?) 125 00000114 E1560007 cmp r6, r7 ; 126 00000118 1A000005 bne RAM_tally_done ; R8 still set correctly 127 0000011C 128 0000011C E1E00006 mvn r0, r6 ; Values same - coincidence? 129 00000120 E5840000 str r0, [r4] ; Store different value 130 00000124 E5957000 ldr r7, [r5] ; Read value from RAM #1 (?) 131 00000128 E5846000 str r6, [r4] ; Restore old value 132 0000012C E1500007 cmp r0, r7 ; Aliasing? 133 00000130 134 00000130 01A08005 moveq r8, r5 ; Yes - just one RAM after a ll ARM Macro Assembler Page 19 135 00000134 136 00000134 E2488201 RAM_tally_done sub r8, r8, #RAM_base ; R8 now holds RAM size 137 00000138 138 00000138 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 139 00000138 ; R8 now holds length of off-chip RAM 140 00000138 141 00000138 EB00015E bl init_LCD ; R0 indicates LCD presence 142 0000013C E1A09000 mov r9, r0 ; 143 00000140 144 00000140 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 145 00000140 ; R12 still holds startup option 146 00000140 147 00000140 E59FB46C ldr r11, Lit_PIO_base ; Point at PIO 148 00000144 E21C60F0 ands r6, r12, #&F0 ; Get boot option w/o unwa nted bits 149 00000148 1A000002 bne standard_boot ; 150 0000014C 151 0000014C E59B003C ldr r0, [r11, #PIO_PDSR] ; If boot #0 152 00000150 E3100701 tst r0, #AT91_Spartan_init ; Test right hand button 153 00000154 0A0001F8 beq ROM_loader_emergency ; If pressed ... 154 00000158 ; This allows the user to start the ROM loader 155 00000158 ; even if "boot_table" has been corrupted. 156 00000158 157 00000158 E3A0A901 standard_boot mov r10, #boot_table_address ; Offset in the Flash 158 0000015C E28AA302 add r10, r10, #ROM_base ; 159 00000160 160 00000160 E08AA206 add r10, r10, r6, lsl #(boot_table_shifts - 4) ; <7:4> 161 00000164 ; See: "boot_table_entry_length" 162 00000164 163 00000164 E59F245C ldr r2, Lit_code ; "Magic Number" 164 00000168 E59A1000 ldr r1, [r10] ; 165 0000016C E1510002 cmp r1, r2 ; 166 00000170 1A000071 bne Boot_not_found ; Magic number not discov ered 167 00000174 168 00000174 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 169 00000174 ; Begin customising system for selected application 170 00000174 171 00000174 E59A7004 ldr r7, [r10, #Btab_flags] ; Get startup options 172 00000178 173 00000178 E3A00000 mov r0, #0 ; LEDs disabled by default 174 0000017C E3170004 tst r7, #BtFlg_LED_on ; from startup tables 175 00000180 13800101 orrne r0, r0, #AT91_LED_En ; LED enable 176 00000184 E3170002 tst r7, #BtFlg_LCD_light ; 177 00000188 13800601 orrne r0, r0, #AT91_LCD_light ARM Macro Assembler Page 20 ; LCD backlight enable 178 0000018C E58B0034 str r0, [r11, #PIO_CODR] ; Clear outputs to enable 179 00000190 180 00000190 ; Checksum ROM block if required 181 00000190 E59A1010 ldr r1, [r10, #Btab_ROM_start] 182 00000194 E59A2014 ldr r2, [r10, #Btab_ROM_length] 183 00000198 E2811302 add r1, r1, #ROM_base ; True address of ROM block start 184 0000019C E3170010 tst r7, #BtFlg_ROM_check ; 185 000001A0 1B000081 blne ROM_checksum ; Returns Validity in R0 186 000001A4 ; What do we do (/flash) on an error? @@@ 187 000001A4 188 000001A4 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 189 000001A4 ; Check for FPGA configurations 190 000001A4 191 000001A4 E59A0020 ldr r0, [r10, #Btab_spartan_data] ; Spartan definition block 192 000001A8 E2800302 add r0, r0, #ROM_base ; Offset => pointer 193 000001AC E5901000 ldr r1, [r0] ; "Magic number" 194 000001B0 E59F2414 ldr r2, Lit_FPGA ; 195 000001B4 E1510002 cmp r1, r2 ; 196 000001B8 0B000105 bleq spartan_load ; 197 000001BC 198 000001BC 199 000001BC E59A0028 ldr r0, [r10, #Btab_virtex_data] ; Virtex definition block 200 000001C0 E2800302 add r0, r0, #ROM_base ; Offset => pointer 201 000001C4 E5901000 ldr r1, [r0] ; "Magic number" 202 000001C8 E59F23FC ldr r2, Lit_FPGA ; 203 000001CC E1510002 cmp r1, r2 ; 204 000001D0 0B00011E bleq virtex_load ; 205 000001D4 206 000001D4 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 207 000001D4 208 000001D4 ; Maybe clear off-chip RAM 209 000001D4 ; Takes significant time so placed before startup messag e printed 210 000001D4 E3170C02 tst r7, #BtFlg_RAM_clr_ext ; Requested by user? 211 000001D8 031C0001 tsteq r12, #1 ; Power up reset? 212 000001DC 1B00007B blne RAM_clr_ext ; Clear off-chip RAM if eith er 213 000001E0 214 000001E0 ; Send LCD message 215 000001E0 E3170001 tst r7, #BtFlg_LCD_message ; LCD message required? 216 000001E4 13590000 cmpne r9, #FALSE ; Check for LCD absence 217 000001E8 128A0030 addne r0, r10, #Btab_LCD_message 218 000001EC 1B000177 blne print_str_LCD ; If flag set and LCD pres ent 219 000001F0 220 000001F0 ; Maybe clear on-chip RAM 221 000001F0 ; Placed here to be after any stack usage 222 000001F0 E3170C01 tst r7, #BtFlg_RAM_clr_int ; Requested by user? 223 000001F4 031C0001 tsteq r12, #1 ; Power up reset? ARM Macro Assembler Page 21 224 000001F8 1B000077 blne RAM_clr_int ; 225 000001FC 226 000001FC ; Implant any on chip RAM image 227 000001FC E59A1008 ldr r1, [r10, #Btab_RAM_start] ; RAM image start offset 228 00000200 E2811302 add r1, r1, #ROM_base ; RAM image start address 229 00000204 E3A02000 mov r2, #FASTRAM_base ; (a.k.a. 00000000) 230 00000208 E59A300C ldr r3, [r10, #Btab_RAM_length] ; RAM image length 231 0000020C 232 0000020C E3530000 cmp r3, #0 ; 233 00000210 1B00005E blne Copy_to_RAM ; Copies whole words (stackl ess) 234 00000214 235 00000214 E59F1398 ldr r1, Lit_PIO_base ; This sets nice default 236 00000218 E3A000FF mov r0, #&FF ; after LCD print 237 0000021C E5810034 str r0, [r1, #PIO_CODR] ; PIO outputs [7:0] to 0 238 00000220 E5810010 str r0, [r1, #PIO_OER] ; and enable them 239 00000224 240 00000224 ; Set up stack pointers 241 00000224 ; R1 = size of internal RAM (= top of internal RAM) 242 00000224 E10F0000 mrs r0, cpsr ; 243 00000228 E3C0000F bic r0, r0, #Mode_bits ; Clear mode bits 244 0000022C 245 0000022C E1A0100D mov r1, sp ; Default Supervisor SP 246 00000230 E2411C02 sub r1, r1, #Supervisor_stack ; Reserve space 247 00000234 248 00000234 E3802001 orr r2, r0, #FIQ_mode ; 249 00000238 E121F002 msr cpsr_c, r2 ; 250 0000023C E1A00000 nop ; 251 00000240 E1A0D001 mov sp, r1 ; Default FIQ SP 252 00000244 E2411080 sub r1, r1, #FIQ_stack ; 253 00000248 254 00000248 E3802002 orr r2, r0, #IRQ_mode ; 255 0000024C E121F002 msr cpsr_c, r2 ; 256 00000250 E1A00000 nop ; 257 00000254 E1A0D001 mov sp, r1 ; Default IRQ SP 258 00000258 E2411080 sub r1, r1, #IRQ_stack ; 259 0000025C 260 0000025C E3802007 orr r2, r0, #Abort_mode ; 261 00000260 E121F002 msr cpsr_c, r2 ; 262 00000264 E1A00000 nop ; 263 00000268 E1A0D001 mov sp, r1 ; Default abort SP 264 0000026C E2411080 sub r1, r1, #Abort_stack ; 265 00000270 266 00000270 E380200B orr r2, r0, #Undefined_mode ; 267 00000274 E121F002 msr cpsr_c, r2 ; 268 00000278 E1A00000 nop ; 269 0000027C E1A0D001 mov sp, r1 ; Default undef. SP 270 00000280 E2411080 sub r1, r1, #Undefined_stack ; 271 00000284 272 00000284 E380200F orr r2, r0, #System_mode ; 273 00000288 E121F002 msr cpsr_c, r2 ; 274 0000028C E1A00000 nop ; 275 00000290 E1A0D001 mov sp, r1 ; Default User SP ARM Macro Assembler Page 22 276 00000294 ; No space specified 277 00000294 278 00000294 E3802003 orr r2, r0, #Supervisor_mode ; We need an SPSR 279 00000298 E121F002 msr cpsr_c, r2 ; 280 0000029C E1A00000 nop ; 281 000002A0 282 000002A0 E59AB01C ldr r11, [r10, #Btab_exec_CPSR] ; R11 read again below 283 000002A4 E169F00B msr spsr_fc, r11 ; Save user's mode, flags e tc. 284 000002A8 285 000002A8 E1A0000A mov r0, r10 ; R10 points at config. tabl e 286 000002AC E1A0100D mov r1, sp ; SP is at top of RAM 287 000002B0 288 000002B0 E3A02201 mov r2, #RAM_base ; 289 000002B4 E1A03008 mov r3, r8 ; Off-chip RAM length 290 000002B8 E59A4020 ldr r4, [r10, #Btab_spartan_data] ; Spartan definition block 291 000002BC E59A5028 ldr r5, [r10, #Btab_virtex_data] ; Virtex definition block 292 000002C0 293 000002C0 E3A07000 mov r7, #0 ; 294 000002C4 E3790001 cmp r9, #TRUE ; 295 000002C8 03877001 orreq r7, r7, #LCD_present_flag ; Flag LCD presence 296 000002CC ; @@@ More flags? 297 000002CC 298 000002CC E31C0001 tst r12, #1 ; Power up reset? 299 000002D0 13877C01 orrne r7, r7, #Power_up_flag ; Flag Power up reset 300 000002D4 301 000002D4 E59F82E0 ldr r8, Lit_SF_base ; Check if watchdog reset 302 000002D8 E5988008 ldr r8, [r8, #SF_RSR] ; 303 000002DC E3580053 cmp r8, #Watchdogged_code ; 304 000002E0 03877C02 orreq r7, r7, #Watchdogged_flag ; Flag Watchdog reset 305 000002E4 306 000002E4 E51F628C ldr r6, Version_ID ; Boot code version number 307 000002E8 308 000002E8 E59A8010 ldr r8, [r10, #Btab_ROM_start] ; ROM code start address 309 000002EC E59A9018 ldr r9, [r10, #Btab_exec_offset] ; Code entry offset 310 000002F0 311 000002F0 E59AA004 ldr r10, [r10, #Btab_flags] ; Get startup options again 312 000002F4 E31A0008 tst r10, #BtFlg_RAM_boot ; 313 000002F8 0088A009 addeq r10, r8, r9 ; Starting in ROM 314 000002FC 028AA302 addeq r10, r10, #ROM_base ; ROM code start address 315 00000300 11A0A009 movne r10, r9 ; Starting in RAM - use offs et only 316 00000304 317 00000304 E10FC000 mrs r12, cpsr ; Keep current mode 318 00000308 E20BB00F and r11, r11, #Mode_bits ARM Macro Assembler Page 23 ; R11 still holds app's CPSR 319 0000030C E35B0001 cmp r11, #FIQ_mode ; Is a different R8 wanted? 320 00000310 321 00000310 038BB0D0 orreq r11, r11, #&D0 ; Keep other bits sensible 322 00000314 0121F00B msreq cpsr_c, r11 ; Flip to FIQ mode if requir ed 323 00000318 E1A00000 nop ; 324 0000031C 325 0000031C E59F8010 ldr r8, serial_no_ptr ; Get pointer to seria l number 326 00000320 E5988000 ldr r8, [r8] ; Get serial number 327 00000324 328 00000324 E59F900C ldr r9, clock_speed ; Get the processor speed 329 00000328 330 00000328 E121F00C msr cpsr_c, r12 ; Restore supervisor mode 331 0000032C E1A00000 nop ; (just in case app. = FIQ) 332 00000330 333 00000330 E1B0F00A movs pc, r10 ; Go! also `restore' CPSR 334 00000334 335 00000334 336 00000334 08003FFC serial_no_ptr DCD ROM_base + Serial_number_addr 337 00000338 00200000 clock_speed DCD clock_rate 338 0000033C 339 0000033C ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 340 0000033C ; At dispatch to application the registers are set up as follows: 341 0000033C ; 342 0000033C ; R0 = Boot configuration table entry address 343 0000033C ; R1 = Size of internal RAM 344 0000033C ; R2 = Base address of external RAM 345 0000033C ; R3 = Length of external RAM 346 0000033C ; R4 = Spartan definition block 347 0000033C ; R5 = Virtex definition block 348 0000033C ; R6 = Boot code version number Developer (8 bits) 349 0000033C ; Version (8 bits) 350 0000033C ; Date (5/4/7 bits) 351 0000033C ; R7 = Bit coded flags <0> = LCD present 352 0000033C ; Ethernet, Spartan, Virtex presence ... @@@ 353 0000033C ; <8> = Power up reset 354 0000033C ; <9> = Watchdog reset 355 0000033C ; R8 = Board serial number 356 0000033C ; R9 = Processor clock speed (hard coded in this progra mme) 357 0000033C ; SPs = All set in internal RAM with stack sizes specifi ed by the header file 358 0000033C ; 359 0000033C ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 360 0000033C ; R9 still holds LCD presence flag 361 0000033C ARM Macro Assembler Page 24 362 0000033C E3790001 Boot_not_found cmp r9, #TRUE ; Check for LCD presence 363 00000340 E28F0038 adr r0, No_boot_message ; 364 00000344 0B000121 bleq print_str_LCD ; Print message if possible 365 00000348 366 00000348 E59FB264 ldr r11, Lit_PIO_base ; 367 0000034C E3A00101 mov r0, #AT91_LED_En ; LEDs on 368 00000350 E58B0034 str r0, [r11, #PIO_CODR] ; Low to enable 369 00000354 370 00000354 E3A000FF mov r0, #&FF ; All LEDs 371 00000358 E58B0010 str r0, [r11, #PIO_OER] ; Bottom eight bits as outputs 372 0000035C 373 0000035C E58B0030 Boot_not_found1 str r0, [r11, #PIO_SODR] ; Set LEDs 374 00000360 EB000002 bl No_boot_delay ; 375 00000364 E58B0034 str r0, [r11, #PIO_CODR] ; Clear LEDs 376 00000368 EB000000 bl No_boot_delay ; 377 0000036C EAFFFFFA b Boot_not_found1 ; 378 00000370 379 00000370 E3A01802 No_boot_delay mov r1, #No_boot_SW_delay ; Really should us e timer ... 380 00000374 E2511001 No_boot_delay1 subs r1, r1, #1 ; @@@ 381 00000378 8AFFFFFD bhi No_boot_delay1 ; 382 0000037C E1A0F00E mov pc, lr 383 00000380 384 00000380 0C 4E 6F 20 62 6F 6F 74 20 66 6F 75 6E 64 00 No_boot_message DCB cFF,"No boot found",ttr 385 0000038F 386 0000038F ;------------------------------------------------------- ----------------------- 387 0000038F ; Copy memory from R1 to R2 length R3 bytes (whole words only) 388 0000038F ; Corrupts R0-R3 389 0000038F 390 0000038F 00 E2833003 Copy_to_RAM add r3, r3, #3 ; In case of partial words 391 00000394 E1A03123 mov r3, r3, lsr #2 ; Number of words 392 00000398 E4910004 Copy_to_RAM1 ldr r0, [r1], #4 ; 393 0000039C E4820004 str r0, [r2], #4 ; 394 000003A0 E2533001 subs r3, r3, #1 ; 395 000003A4 8AFFFFFB bhi Copy_to_RAM1 ; 396 000003A8 E1A0F00E mov pc, lr ; 397 000003AC 398 000003AC ;------------------------------------------------------- ARM Macro Assembler Page 25 ----------------------- 399 000003AC ; R1 is (true) address, R2 is length in bytes 400 000003AC ; Returns pass/fail in R0 401 000003AC ; Corrupts R1-R3 402 000003AC 403 000003AC E3A00000 ROM_checksum mov r0, #0 ; Accumulator 404 000003B0 405 000003B0 E4D13001 ROM_checksum1 ldrb r3, [r1], #1 ; 406 000003B4 E2522001 subs r2, r2, #1 ; Here in case of load delay 407 000003B8 E0800003 add r0, r0, r3 ; Accumulate 408 000003BC 8AFFFFFB bhi ROM_checksum1 ; 409 000003C0 410 000003C0 E31000FF tst r0, #&FF ; Totals to 00? 411 000003C4 03E00000 moveq r0, #TRUE ; 412 000003C8 13A00000 movne r0, #FALSE ; 413 000003CC E1A0F00E mov pc, lr ; 414 000003D0 415 000003D0 ;------------------------------------------------------- ----------------------- 416 000003D0 ; Zero any off- or on- chip RAM. 417 000003D0 ; On entry R8/R13 (respectively) holds RAM length 418 000003D0 ; Corrupts R1-R3 419 000003D0 420 000003D0 E1B02128 RAM_clr_ext movs r2, r8, lsr #2 ; Length in words 421 000003D4 01A0F00E moveq pc, lr ; Return if no RAM 422 000003D8 EA000000 b RAM_clr ; 423 000003DC 424 000003DC E1A0212D RAM_clr_int mov r2, r13, lsr #2 ; Length in words 425 000003E0 426 000003E0 E3A01000 RAM_clr mov r1, #0 ; 427 000003E4 E3A03201 mov r3, #RAM_base ; 428 000003E8 E4831004 RAM_clr_1 str r1, [r3], #4 ; 429 000003EC E2522001 subs r2, r2, #1 ; 430 000003F0 8AFFFFFC bhi RAM_clr_1 ; 431 000003F4 E1A0F00E mov pc, lr ; 432 000003F8 433 000003F8 ; Needs testing @@@ 434 000003F8 ; Needs speeding up too - Try an STM @@@ 435 000003F8 436 000003F8 ;------------------------------------------------------- ----------------------- 437 000003F8 ; Initialise on-chip I/O 438 000003F8 ; This routine runs RAMless 439 000003F8 ; Corrupts R0-R3, R13, R14 440 000003F8 441 000003F8 E1A0D00E Device_init ARM Macro Assembler Page 26 mov r13, lr ; Save return address 442 000003FC 443 000003FC E28F1048 adr r1, EBI_setup ; Definitions table 444 00000400 EB00000A bl dev_init ; Set up EBI 445 00000404 446 00000404 E28F1090 adr r1, PIO_setup ; Definitions table 447 00000408 EB000008 bl dev_init ; Set up PIO 448 0000040C 449 0000040C E28F10E0 adr r1, PS_setup ; Definitions table 450 00000410 EB000006 bl dev_init ; Set up PS 451 00000414 452 00000414 E28F10FC adr r1, WD_setup ; Definitions table 453 00000418 EB000004 bl dev_init ; Set up WD 454 0000041C 455 0000041C E28F1E11 adr r1, US0_setup ; Definitions table 456 00000420 EB000002 bl dev_init ; Set up US0 457 00000424 458 00000424 E28F1F52 adr r1, US1_setup ; Definitions table 459 00000428 EB000000 bl dev_init ; Set up US1 460 0000042C 461 0000042C E1A0F00D mov pc, r13 ; Return 462 00000430 463 00000430 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 464 00000430 ; R4 is true to indicate UART - calculate baud rate 465 00000430 ; Corrupts R0-R3 466 00000430 467 00000430 E4913004 dev_init ldr r3, [r1], #4 ; Get base address 468 00000434 ; Pass setup data in R1 469 00000434 E4912004 dev_loop ldr r2, [r1], #4 ; Register offset 470 00000438 E1B02002 movs r2, r2 ; See if negative 471 0000043C 41A0F00E movmi pc, lr ; yes - terminate 472 00000440 E4910004 ldr r0, [r1], #4 ; Get data value 473 00000444 E7830002 str r0, [r3, r2] ; Store value 474 00000448 EAFFFFF9 b dev_loop ; and repeat ... 475 0000044C 476 0000044C ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 477 0000044C ; ROM speed set too tight for writes @32MHz - Flash load er slows this down 478 0000044C 479 0000044C ; Chip select bus addresses and region widths & speeds 480 0000044C FFE00000 EBI_setup DCD EBI_base 481 00000450 00000000 DCD EBI_CSR0 ; Chip select 0 482 00000454 080023B5 DCD (ROM_base :AND: &FFF00000) :OR: CSEN :OR : TDF1 :OR: Pg64M :OR: NWS6 :OR: DBW16 483 00000458 ; DCD (ROM_base :AND: &FFF00000) :OR: CSEN :OR: TDF1 :O R: Pg64M :OR: NWS4 :OR: DBW16 484 00000458 ; ROM set to 4 wait states; okay for writing, sub-optima l for reading. 485 00000458 ; Fix in Flash download option @@@ 486 00000458 00000004 DCD EBI_CSR1 ; Chip select 1 487 0000045C 100033B1 DCD (RAM_base :AND: &FFF00000) :OR: CSEN :OR ARM Macro Assembler Page 27 : BAT :OR: TDF1 :OR: Pg64M :OR: NWS5 :OR: DBW16 488 00000460 00000008 DCD EBI_CSR2 ; Chip select 2 489 00000464 20003382 DCD (VIRTEX_base :AND: &FFF00000) :OR: CSEN :OR: BAT :OR: TDF1 :OR: Pg64M :OR: DBW8 490 00000468 0000000C DCD EBI_CSR3 ; Chip select 3 491 0000046C 3000343D DCD (ETHERNET_base :AND: &FFF00000) :OR: CSE N :OR: BAT :OR: TDF2 :OR: Pg1M :OR: NWS8 :OR: DBW16 492 00000470 00000010 DCD EBI_CSR4 ; Chip select 4 493 00000474 40003232 DCD (SPARTAN_base :AND: &FFF00000) :OR: CSEN :OR: BAT :OR: TDF1 :OR: Pg1M :OR: NWS5 :OR: DBW8 494 00000478 00000014 50000000 DCD EBI_CSR5, &50000000 ; Chip select 5 495 00000480 00000018 60000000 DCD EBI_CSR6, &60000000 ; Chip select 6 496 00000488 0000001C 70000000 DCD EBI_CSR7, &70000000 ; Chip select 7 497 00000490 00000024 00000004 DCD EBI_MCR, &00000004 ; Memory Control 498 00000498 ; A[22:20], CS4 499 00000498 FFFFFFFF DCD DEV_TERMINATE 500 0000049C 501 0000049C ; `Original' bit patterns 502 0000049C ; DCD EBI_CSR0, (ROM_base :AND: &FFF00000) :OR: &021BD 503 0000049C ; DCD EBI_CSR1, (RAM_base :AND: &FFF00000) :OR: &031A5 504 0000049C ; DCD EBI_CSR2, (VIRTEX_base :AND: &FFF00000) :OR: &033 82 505 0000049C ; DCD EBI_CSR4, (SPARTAN_base :AND: &FFF00000) :OR: &03 226 506 0000049C 507 0000049C ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 508 0000049C 509 0000049C FFFF0000 PIO_setup DCD PIO_base 510 000004A0 00000030 40930000 DCD PIO_SODR, &40930000 ; Set Output Data 511 000004A8 ; Xilinx program lines inactive 512 000004A8 00000034 010000FF DCD PIO_CODR, &010000FF ; Clear Output Data 513 000004B0 ; 514 000004B0 00000010 439300FF DCD PIO_OER, &439300FF ; Output Enable 515 000004B8 00000014 000C3E00 DCD PIO_ODR, &000C3E00 ; Output Disable 516 000004C0 00000000 439F3EFF DCD PIO_PER, &439F3EFF ; PIO Enable 517 000004C8 00000004 BC60C100 DCD PIO_PDR, &BC60C100 ; PIO Disable 518 000004D0 00000020 00000000 DCD PIO_IFER, &00000000 ; Input Filter Enable 519 000004D8 00000024 00000000 DCD PIO_IFDR, &00000000 ; Input Filter Disable 520 000004E0 00000040 00000000 DCD PIO_IER, &00000000 ; Interrupt Enable 521 000004E8 00000044 FFFFFFFF DCD PIO_IDR, &FFFFFFFF ; Interrupt Disable ARM Macro Assembler Page 28 522 000004F0 FFFFFFFF DCD DEV_TERMINATE 523 000004F4 524 000004F4 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 525 000004F4 526 000004F4 FFFF4000 PS_setup DCD PS_base 527 000004F8 FFFFFFFF DCD DEV_TERMINATE 528 000004FC 00000000 00000000 DCD PS_CR, &00000000 ; CPU Clock Stop 529 00000504 00000004 0000014C DCD PS_PCER, &0000014C ; Peripheral Clock Enable 530 0000050C 0000000C 00000030 DCD PS_PCSR, &00000030 ; Peripheral Clock Disable 531 00000514 FFFFFFFF DCD DEV_TERMINATE 532 00000518 533 00000518 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 534 00000518 535 00000518 FFFF8000 WD_setup DCD WD_base 536 0000051C FFFFFFFF DCD DEV_TERMINATE 537 00000520 00000000 00002340 DCD WD_OMR, &00002340 ; Overflow Mode 538 00000528 00000004 00006E00 DCD WD_CMR, &00006E00 ; Clock Mode 539 00000530 FFFFFFFF DCD DEV_TERMINATE 540 00000534 541 00000534 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 542 00000534 543 00000534 FFFD0000 US0_setup DCD US0_base 544 00000538 00000000 0000055C DCD US_CR, &0000055C ; USART Control Register 545 00000540 00000004 000408C0 DCD US_MR, &000408C0 ; USART Mode 546 00000548 00000008 00000000 DCD US_IER, &00000000 ; USART Interrupt Enable 547 00000550 0000000C FFFFFFFF DCD US_IDR, &FFFFFFFF ; USART Interrupt Disable 548 00000558 00000020 DCD US_BRGR ; Baud Rate Generator (CD) 549 0000055C 00000068 DCD (2*clock_rate/baud19k2 + 1)/2 550 00000560 00000024 00000000 DCD US_RTOR, &00000000 ; Receiver Time Out 551 00000568 00000028 00000000 DCD US_TTGR, &00000000 ; Transmitter Time Out 552 00000570 FFFFFFFF DCD DEV_TERMINATE 553 00000574 554 00000574 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - ARM Macro Assembler Page 29 - - - - - - - - - - - - 555 00000574 556 00000574 FFFCC000 US1_setup DCD US1_base 557 00000578 00000000 0000055C DCD US_CR, &0000055C ; USART Control Register 558 00000580 00000004 000008C0 DCD US_MR, &000008C0 ; USART Mode 559 00000588 00000008 00000000 DCD US_IER, &00000000 ; USART Interrupt Enable 560 00000590 0000000C FFFFFFFF DCD US_IDR, &FFFFFFFF ; USART Interrupt Disable 561 00000598 00000020 DCD US_BRGR ; Baud Rate Generator (CD) 562 0000059C 00000068 DCD (2*clock_rate/baud19k2 + 1)/2 563 000005A0 00000024 00000000 DCD US_RTOR, &00000000 ; Receiver Time Out 564 000005A8 00000028 00000000 DCD US_TTGR, &00000000 ; Transmitter Time Out 565 000005B0 FFFFFFFF DCD DEV_TERMINATE 566 000005B4 567 000005B4 ;------------------------------------------------------- ----------------------- 568 000005B4 ; Literal pool 569 000005B4 570 000005B4 FFFF0000 Lit_PIO_base DCD PIO_base ; 571 000005B8 FFE00000 Lit_EBI_base DCD EBI_base ; 572 000005BC FFF00000 Lit_SF_base DCD SF_base ; 573 000005C0 574 000005C0 40000000 Lit_Spartan_base DCD SPARTAN_base ; 575 000005C4 20000000 Lit_Virtex_base DCD VIRTEX_base ; 576 000005C8 577 000005C8 ;Lit_boot_table DCD boot_table_address ; 578 000005C8 579 000005C8 43 4F 44 45 Lit_code DCB "CODE" ; 580 000005CC 46 50 47 41 Lit_FPGA DCB "FPGA" ; 581 000005D0 55AA55AA Lit_RAM_test_val DCD &55AA55AA ; 582 000005D4 583 000005D4 ;------------------------------------------------------- ARM Macro Assembler Page 30 ----------------------- 584 000005D4 ; R0 points at config. block 585 000005D4 586 000005D4 E92D580B spartan_load stmfd sp!, {r0,r1,r3,r11,r12,lr} 587 000005D8 E1A0B000 mov r11, r0 ; Configuration definition 588 000005DC 589 000005DC ; Force other PIO bits to correct state before resetting Spartan 590 000005DC E51F0030 ldr r0, Lit_PIO_base ; 591 000005E0 592 000005E0 E3A01502 mov r1, #AT91_Spartan_CS1 ; 593 000005E4 E5801030 str r1, [r0, #PIO_SODR] ; Output high (alway s PIO output) 594 000005E8 595 000005E8 E3A01A03 mov r1, #(AT91_Spartan_HDC :OR: AT91_FPGA_ba ud) 596 000005EC E5801014 str r1, [r0, #PIO_ODR] ; Output disabled 597 000005F0 E5801000 str r1, [r0, #PIO_PER] ; Ensure PIO is used 598 000005F4 ; Sensitive signals floated 599 000005F4 600 000005F4 E3A01801 mov r1, #AT91_Spartan_prog ; Reset Spartan 601 000005F8 E5801034 str r1, [r0, #PIO_CODR] ; Programme pin low (pulse >300ns) 602 000005FC E5801030 str r1, [r0, #PIO_SODR] ; Programme pin high again 603 00000600 604 00000600 605 00000600 E590103C spartan_wtr ldr r1, [r0, #PIO_PDSR] ; PIO pin state 606 00000604 E3110701 tst r1, #AT91_Spartan_init ; 607 00000608 0AFFFFFC beq spartan_wtr ; Wait for Spartan to be rea dy 608 0000060C 609 0000060C E3A01032 mov r1, #50 ; Want >5us delay here 610 00000610 E2511001 spartan_wtr1 subs r1, r1, #1 ; 100ns/loop if in 40MHz 32- bit RAM 611 00000614 1AFFFFFD bne spartan_wtr1 ; 612 00000618 613 00000618 E59B0004 ldr r0, [r11, #FPGA_offset] ; Offset 614 0000061C E59B1008 ldr r1, [r11, #FPGA_length] ; Length 615 00000620 E08BB000 add r11, r11, r0 ; Start of stream 616 00000624 617 00000624 E51FC06C ldr r12, Lit_Spartan_base ; Spartan address 618 00000628 619 00000628 E4DB3001 spartan_strip ldrb r3, [r11], #1 ; Strip header message 620 0000062C E2411001 sub r1, r1, #1 ; 621 00000630 E35300FF cmp r3, #&FF ; until FF found 622 00000634 1AFFFFFB bne spartan_strip ; 623 00000638 624 00000638 E5CC3000 strb r3, [r12] ; First byte of configuratio n 625 0000063C ARM Macro Assembler Page 31 626 0000063C ; Throw config. stream at device 627 0000063C E4DB3001 spartan_loop ldrb r3, [r11], #1 ; Fetch byte & increment a ddress 628 00000640 E5CC3000 strb r3, [r12] ; & programme FPGA 629 00000644 E2511001 subs r1, r1, #1 ; Loop count 630 00000648 1AFFFFFB bne spartan_loop ; 631 0000064C 632 0000064C E8BD980B ldmfd sp!, {r0,r1,r3,r11,r12,pc} 633 00000650 634 00000650 ;------------------------------------------------------- ----------------------- 635 00000650 ; R0 points at config. block 636 00000650 637 00000650 E92D580B virtex_load stmfd sp!, {r0,r1,r3,r11,r12,lr} 638 00000654 E1A0B000 mov r11, r0 ; Configuration definition 639 00000658 640 00000658 ; Force other PIO bits to correct state before resetting Virtex 641 00000658 E51F00AC ldr r0, Lit_PIO_base ; 642 0000065C 643 0000065C E3A01802 mov r1, #AT91_Virtex_prog ; Reset Virtex 644 00000660 E5801034 str r1, [r0, #PIO_CODR] ; Programme pin low (pulse width min? @@@) 645 00000664 E5801030 str r1, [r0, #PIO_SODR] ; Programme pin high again 646 00000668 647 00000668 648 00000668 E590103C virtex_wtr ldr r1, [r0, #PIO_PDSR] ; PIO pin state 649 0000066C E3110702 tst r1, #AT91_Virtex_init ; 650 00000670 0AFFFFFC beq virtex_wtr ; Wait for Virtex to be read y 651 00000674 652 00000674 ; Next delay necessary ??? @@@ 653 00000674 E3A01032 mov r1, #50 ; Want >5us delay here 654 00000678 E2511001 virtex_wtr1 subs r1, r1, #1 ; 100ns/loop if in 40MHz 32- bit RAM 655 0000067C 1AFFFFFD bne virtex_wtr1 ; 656 00000680 657 00000680 E59B0004 ldr r0, [r11, #FPGA_offset] ; Offset 658 00000684 E59B1008 ldr r1, [r11, #FPGA_length] ; Length 659 00000688 E08BB000 add r11, r11, r0 ; Start of stream 660 0000068C 661 0000068C E51FC0D0 ldr r12, Lit_Virtex_base ; Virtex address 662 00000690 663 00000690 E4DB3001 virtex_strip ldrb r3, [r11], #1 ; Strip header message 664 00000694 E2411001 sub r1, r1, #1 ; 665 00000698 E35300FF cmp r3, #&FF ; until FF found 666 0000069C 1AFFFFFB bne virtex_strip ; 667 000006A0 ARM Macro Assembler Page 32 668 000006A0 E5CC3000 strb r3, [r12] ; First byte of configuratio n 669 000006A4 670 000006A4 ; Throw config. stream at device 671 000006A4 E4DB3001 virtex_loop ldrb r3, [r11], #1 ; Fetch byte & increment a ddress 672 000006A8 E5CC3000 strb r3, [r12] ; & programme FPGA 673 000006AC E2511001 subs r1, r1, #1 ; Loop count 674 000006B0 1AFFFFFB bne virtex_loop ; 675 000006B4 676 000006B4 E8BD980B ldmfd sp!, {r0,r1,r3,r11,r12,pc} 677 000006B8 678 000006B8 ;------------------------------------------------------- ----------------------- 679 000006B8 680 000006B8 E92D401C init_LCD stmfd sp!, {r2-r4, lr} ; 681 000006BC 682 000006BC E51F4110 ldr r4, Lit_PIO_base ; 683 000006C0 684 000006C0 E3A000FF mov r0, #&FF ; Data bus bits 685 000006C4 E5840014 str r0, [r4, #PIO_ODR] ; Disable data output bus 686 000006C8 687 000006C8 E3A0050E mov r0, #(AT91_LCD_RS :OR: AT91_LCD_En :OR: AT91_LCD_RW) 688 000006CC ; All control bits 689 000006CC E5C40034 strb r0, [r4, #PIO_CODR] ; Control bits inactive 690 000006D0 E5C40010 strb r0, [r4, #PIO_OER] ; Control out 691 000006D4 692 000006D4 E28F30A8 adr r3, LCD_init_table ; 693 000006D8 694 000006D8 E4D30001 init_LCD_1 ldrb r0, [r3], #1 ; Address 695 000006DC E35000FF cmp r0, #&FF ; Table terminator? 696 000006E0 0A00000A beq init_LCD_done ; 697 000006E4 698 000006E4 E3100001 tst r0, #1 ; Control or data? 699 000006E8 E4D30001 ldrb r0, [r3], #1 ; Data 700 000006EC 1A000001 bne init_LCD_1a ; 701 000006F0 EB000068 bl LCD_ctrl_wr ; Send byte to LCD control r eg. 702 000006F4 EA000000 b init_LCD_1b ; 703 000006F8 704 000006F8 EB000061 init_LCD_1a bl LCD_data_wr ; Send byte to LCD data reg. 705 000006FC 706 000006FC E4D32001 init_LCD_1b ldrb r2, [r3], #1 ; Delay 707 00000700 708 00000700 EB00001B ARM Macro Assembler Page 33 init_LCD_2 bl init_LCD_delay ; Bide a while 709 00000704 E2522001 subs r2, r2, #1 ; Count from table 710 00000708 8AFFFFFC bhi init_LCD_2 ; 711 0000070C 712 0000070C EAFFFFF1 b init_LCD_1 ; 713 00000710 714 00000710 EB000077 init_LCD_done bl LCD_data_rd ; 715 00000714 E350005A cmp r0, #&5A ; See if test character pres ent 716 00000718 13A00000 movne r0, #FALSE ; 717 0000071C 18BD801C ldmnefd sp!, {r2-r4, pc} ; Zero flag clear if LC D absent 718 00000720 719 00000720 EB00004A bl LCD_wtr ; Can now do this properly 720 00000724 E3A00001 mov r0, #&01 ; Clear screen 721 00000728 EB00005A bl LCD_ctrl_wr ; Send byte to LCD control r eg. 722 0000072C 723 0000072C EB000047 bl LCD_wtr ; 724 00000730 E3A00048 mov r0, #&48 ; Point at CGRAM character # 1 725 00000734 EB000057 bl LCD_ctrl_wr ; Send byte to LCD control r eg. 726 00000738 727 00000738 E28F1066 adr r1, character_defns ; 728 0000073C E4D12001 ldrb r2, [r1], #1 ; Get length 729 00000740 730 00000740 E4D10001 CGRAM_load ldrb r0, [r1], #1 ; Get byte 731 00000744 EB000041 bl LCD_wtr ; 732 00000748 EB00004D bl LCD_data_wr ; 733 0000074C E2522001 subs r2, r2, #1 ; 734 00000750 8AFFFFFA bhi CGRAM_load ; 735 00000754 736 00000754 EB00003D bl LCD_wtr ; 737 00000758 E3A00080 mov r0, #&80 ; Point at DDRAM (start) 738 0000075C EB00004D bl LCD_ctrl_wr ; Send byte to LCD control r eg. 739 00000760 740 00000760 EB00003A bl LCD_wtr ; 741 00000764 E3A0000C mov r0, #&0C ; Display on, cursor off 742 00000768 EB00004A bl LCD_ctrl_wr ; Send byte to LCD control r eg. 743 0000076C 744 0000076C E3E00000 mov r0, #TRUE ; Signal LCD present 745 00000770 E8BD801C ldmfd sp!, {r2-r4, pc} ; 746 00000774 747 00000774 748 00000774 E3A00064 init_LCD_delay mov r0, #LCD_int_SW_delay ; Each iteration ~ 100us (100ns ROM) 749 00000778 E2500001 init_LCD_dly1 subs r0, r0, #1 ; 5 instructions fetched/loo ARM Macro Assembler Page 34 p 750 0000077C 91A0F00E movls pc, lr ; 751 00000780 EAFFFFFC b init_LCD_dly1 ; 752 00000784 753 00000784 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 754 00000784 ; LCD initialisation table 755 00000784 ; Uses a specified delay (iteration >~1us from ROM) in c ase LCD not present 756 00000784 757 00000784 00 30 01 LCD_init_table DCB 0, &30, 1 ; Use 8-bit interface 758 00000787 00 30 01 DCB 0, &30, 1 ; Use 8-bit interface 759 0000078A 00 30 01 DCB 0, &30, 1 ; Use 8-bit interface 760 0000078D 00 00 01 DCB 0, &00, 1 ; NOP - seems to help 761 00000790 00 3C 01 DCB 0, &3C, 1 ; 8-bit interface, 2 lines 762 00000793 00 08 01 DCB 0, &08, 1 ; Display off, cursor off 763 00000796 00 06 01 DCB 0, &06, 1 ; Cursor moves right, no scr oll 764 00000799 00 80 01 DCB 0, &80, 1 ; RAM address 0 765 0000079C 01 5A 01 DCB 1, &5A, 1 ; Test character #0 766 0000079F 01 75 01 DCB 1, &75, 1 ; Test character #1 767 000007A2 00 80 01 DCB 0, &80, 1 ; RAM address 0 again 768 000007A5 FF DCB &FF 769 000007A6 770 000007A6 771 000007A6 ; Dog kennel definition 772 000007A6 28 character_defns DCB 5 * 8 ; Length 773 000007A7 01 03 0E 0C 18 19 19 19 DCB &01,&03,&0E,&0C,&18,&19,&19,&19 ; Top left 774 000007AF 10 08 15 03 11 15 15 15 DCB &10,&08,&15,&03,&11,&15,&15,&15 ; Top right 775 000007B7 18 18 19 1A 1A 18 18 08 DCB &18,&18,&19,&1A,&1A,&18,&18,&08 ; Bottom left 776 000007BF 00 18 0C 06 06 06 06 02 DCB &00,&18,&0C,&06,&06,&06,&06,&02 ; Bottom right 777 000007C7 01 02 02 0F 16 0A 02 04 DCB &01,&02,&02,&0F,&16,&0A,&02,&04 ; "of" 778 000007CF 779 000007CF 00 ALIGN 780 000007D0 781 000007D0 ;------------------------------------------------------- ----------------------- 782 000007D0 783 000007D0 E92D4003 print_str_LCD stmfd sp!, {r0-r1,lr} ; 784 000007D4 E1A01000 mov r1, r0 ; String pointer ARM Macro Assembler Page 35 785 000007D8 E4D10001 print_str_LCD_1 ldrb r0, [r1], #1 ; Load, auto-increment 786 000007DC E3500000 cmp r0, #ttr ; 787 000007E0 08BD8003 ldmeqfd sp!, {r0-r1,pc} ; Conditional return 788 000007E4 EB000000 bl print_ch_LCD ; 789 000007E8 EAFFFFFA b print_str_LCD_1 ; 790 000007EC 791 000007EC 792 000007EC E92D4000 print_ch_LCD stmfd sp!, {lr} ; 793 000007F0 EB000016 bl LCD_wtr ; 794 000007F4 E350000D cmp r0, #cCR ; 795 000007F8 0A000005 beq print_ctrl_ch1 ; 796 000007FC E350000C cmp r0, #cFF ; 797 00000800 0A000007 beq print_ctrl_ch2 ; 798 00000804 E350000A cmp r0, #cLF ; 799 00000808 0A000009 beq print_ctrl_ch3 ; 800 0000080C EB00001C bl LCD_data_wr ; 801 00000810 E8BD8000 ldmfd sp!, {pc} ; 802 00000814 803 00000814 E92D0001 print_ctrl_ch1 stmfd sp!, {r0} ; 804 00000818 E3A00002 mov r0, #&02 ; Home cursor 805 0000081C EB00001D bl LCD_ctrl_wr ; 806 00000820 E8BD8001 ldmfd sp!, {r0, pc} ; 807 00000824 808 00000824 E92D0001 print_ctrl_ch2 stmfd sp!, {r0} ; 809 00000828 E3A00001 mov r0, #&01 ; Clear screen 810 0000082C EB000019 bl LCD_ctrl_wr ; 811 00000830 E8BD8001 ldmfd sp!, {r0, pc} ; 812 00000834 813 00000834 E92D0001 print_ctrl_ch3 stmfd sp!, {r0} ; Swap text lines & CR 814 00000838 EB000028 bl LCD_ctrl_rd ; Get current DDRAM address 815 0000083C E2200040 eor r0, r0, #&40 ; Other line 816 00000840 E3C0003F bic r0, r0, #&3F ; at the start 817 00000844 E3800080 orr r0, r0, #&80 ; Command 818 00000848 EB000012 bl LCD_ctrl_wr ; 819 0000084C E8BD8001 ldmfd sp!, {r0, pc} ; 820 00000850 821 00000850 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 822 00000850 823 00000850 E92D4011 LCD_wtr stmfd sp!, {r0, r4, lr} ; 824 00000854 E51F42A8 ldr r4, Lit_PIO_base ; 825 00000858 826 00000858 E3A00502 mov r0, #AT91_LCD_RS ; Data bus defaults to input 827 0000085C E5840034 str r0, [r4, #PIO_CODR] ; Control register 828 00000860 E3A00402 mov r0, #AT91_LCD_RW ; 829 00000864 E5840030 str r0, [r4, #PIO_SODR] ; Read ARM Macro Assembler Page 36 830 00000868 831 00000868 E3A00401 mov r0, #AT91_LCD_En ; LCD Enable pin 832 0000086C 833 0000086C E5840030 LCD_wtr1 str r0, [r4, #PIO_SODR] ; Strobe Enable 834 00000870 E594E03C ldr r14, [r4, #PIO_PDSR] ; Read pin data 835 00000874 E5840034 str r0, [r4, #PIO_CODR] ; 836 00000878 837 00000878 E31E0080 tst r14, #AT91_LCD_busy ; See if busy 838 0000087C 1AFFFFFA bne LCD_wtr1 ; Yes - keep trying 839 00000880 840 00000880 E8BD8011 ldmfd sp!, {r0, r4, pc} ; 841 00000884 842 00000884 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 843 00000884 844 00000884 E92D4002 LCD_data_wr stmfd sp!, {r1, lr} ; Write R0 to LCD data reg ister 845 00000888 E51FE2DC ldr r14, Lit_PIO_base ; 846 0000088C E3A01502 mov r1, #AT91_LCD_RS ; 847 00000890 E58E1030 str r1, [r14, #PIO_SODR] ; Data register 848 00000894 EA000003 b LCD_wr ; Jump to write ... 849 00000898 850 00000898 E92D4002 LCD_ctrl_wr stmfd sp!, {r1, lr} ; Write R0 to LCD control register 851 0000089C E51FE2F0 ldr r14, Lit_PIO_base ; 852 000008A0 E3A01502 mov r1, #AT91_LCD_RS ; 853 000008A4 E58E1034 str r1, [r14, #PIO_CODR] ; Control register 854 000008A8 ; Fall into write ... 855 000008A8 856 000008A8 E20010FF LCD_wr and r1, r0, #&FF ; Just the bottom byte 857 000008AC E58E1030 str r1, [r14, #PIO_SODR] ; Set LCD data bus "1"s 858 000008B0 E22110FF eor r1, r1, #&FF ; 859 000008B4 E58E1034 str r1, [r14, #PIO_CODR] ; Reset LCD data bus "0"s 860 000008B8 861 000008B8 E3A01402 mov r1, #AT91_LCD_RW ; 862 000008BC E58E1034 str r1, [r14, #PIO_CODR] ; Write 863 000008C0 864 000008C0 E3A010FF mov r1, #&FF ; 865 000008C4 E58E1010 str r1, [r14, #PIO_OER] ; Drive LCD data bus 866 000008C8 867 000008C8 E3A01401 mov r1, #AT91_LCD_En 868 000008CC E58E1030 str r1, [r14, #PIO_SODR] ; Strobe Enable 869 000008D0 E58E1034 str r1, [r14, #PIO_CODR] ; 870 000008D4 871 000008D4 E3A010FF mov r1, #&FF ; 872 000008D8 E58E1014 str r1, [r14, #PIO_ODR] ; Disable the data outputs 873 000008DC 874 000008DC E8BD8002 ldmfd sp!, {r1, pc} ; ARM Macro Assembler Page 37 875 000008E0 876 000008E0 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 877 000008E0 878 000008E0 E92D4002 LCD_ctrl_rd stmfd sp!, {r1, lr} ; Read R0 from LCD control register 879 000008E4 E51FE338 ldr r14, Lit_PIO_base ; 880 000008E8 E3A01502 mov r1, #AT91_LCD_RS ; 881 000008EC E58E1034 str r1, [r14, #PIO_CODR] ; Control register 882 000008F0 EA000003 b LCD_rd ; Jump to read ... 883 000008F4 884 000008F4 E92D4002 LCD_data_rd stmfd sp!, {r1, lr} ; Read R0 from LCD data re gister 885 000008F8 E51FE34C ldr r14, Lit_PIO_base ; 886 000008FC E3A01502 mov r1, #AT91_LCD_RS ; 887 00000900 E58E1030 str r1, [r14, #PIO_SODR] ; Data register 888 00000904 ; Fall into ... 889 00000904 890 00000904 E3A01402 LCD_rd mov r1, #AT91_LCD_RW ; 891 00000908 E58E1030 str r1, [r14, #PIO_SODR] ; Read 892 0000090C 893 0000090C E3A010FF mov r1, #&FF ; 894 00000910 E58E1014 str r1, [r14, #PIO_ODR] ; Float LCD data bus 895 00000914 896 00000914 E3A01401 mov r1, #AT91_LCD_En 897 00000918 E58E1030 str r1, [r14, #PIO_SODR] ; Strobe Enable 898 0000091C 899 0000091C E3A00064 mov r0, #100 ; Each iteration ~100us (100 ns ROM) 900 00000920 901 00000920 E1A00000 LCD_rd_1 nop ; 5 instructions fetched/loo p 902 00000924 E2500001 subs r0, r0, #1 ; 903 00000928 8AFFFFFC bhi LCD_rd_1 ; 904 0000092C 905 0000092C E59E003C ldr r0, [r14, #PIO_PDSR] ; Read pins 906 00000930 907 00000930 E58E1034 str r1, [r14, #PIO_CODR] ; Remove strobe 908 00000934 909 00000934 E20000FF and r0, r0, #&FF ; Mask off unwanted bits 910 00000938 911 00000938 E8BD8002 ldmfd sp!, {r1, pc} ; 912 0000093C 913 0000093C ;------------------------------------------------------- ----------------------- 914 0000093C ; In `emergency' copy image to RAM directly 915 0000093C 916 0000093C ROM_loader_emergency 917 0000093C E59F1010 ldr r1, ROM_loader_emergency_start 918 00000940 E2811302 add r1, r1, #ROM_base ; RAM image start address ARM Macro Assembler Page 38 919 00000944 E3A02000 mov r2, #FASTRAM_base ; (a.k.a. 00000000) 920 00000948 E59F3008 ldr r3, ROM_loader_emergency_length 921 0000094C EBFFFE8F bl Copy_to_RAM ; Copies whole words 922 00000950 EA0001A6 b ROM_loader_ROM ; Definable address 923 00000954 924 00000954 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 925 00000954 926 00000954 ROM_loader_emergency_start 927 00000954 00001000 DCD ROM_loader_image_start - Start ; RAM start 928 00000958 ROM_loader_emergency_length 929 00000958 00000434 DCD ROM_loader_image_end - ROM_loader_image_ start 930 0000095C 931 0000095C ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 932 0000095C ; Moved up to leave room for boot code development 933 0000095C ; Address defined externally in link_addresses.s 934 0000095C 935 0000095C 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ARM Macro Assembler Page 39 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ARM Macro Assembler Page 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ARM Macro Assembler Page 41 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ARM Macro Assembler Page 42 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ARM Macro Assembler Page 43 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ARM Macro Assembler Page 44 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ARM Macro Assembler Page 45 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ARM Macro Assembler Page 46 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ARM Macro Assembler Page 47 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ALIGN ROM_loader_image_position, -ROM_loader_b ranch_space 936 00000FF0 937 00000FF0 E3A0F00C ROM_loader_ROM mov pc, #(ROM_loader_RAM - ROM_loader_image_ start) 938 00000FF4 ; Dispatch into RAM image 939 00000FF4 ARM Macro Assembler Page 48 940 00000FF4 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 941 00000FF4 00 00 00 00 00 00 00 00 00 00 00 00 ALIGN ROM_loader_image_position 942 00001000 943 00001000 ROM_loader_image_start ; Start of RAM image 944 00001000 945 00001000 98 946 00001000 FFE00000 DCD EBI_base ; Chip select 0 947 00001004 948 00001004 97 ; ROM set to 4 wait states; okay for writing, sub-optima l for reading. 949 00001004 080023AD DCD (ROM_base :AND: &FFF00000) :OR: CSEN :OR : TDF1 :OR: Pg64M :OR: NWS4 :OR: DBW16 950 00001008 951 00001008 FFFD0000 Prog_host_link DCD US0_base 952 0000100C ;Prog_host_link DCD US1_base 953 0000100C 954 0000100C 955 0000100C E51F0014 ROM_loader_RAM ldr r0, %b98 ; EBI_base 956 00001010 E51F1014 ldr r1, %b97 ; New setting 957 00001014 E5801000 str r1, [r0, #EBI_CSR0] ; Downcheck the Flas h bus speed 958 00001018 959 00001018 960 00001018 ; @@@ Really ... 961 00001018 ; Set the two ports to different baud rates (115k2, 9600 ?) 962 00001018 ; Listen to each and lock onto one (into R11) 963 00001018 964 00001018 965 00001018 E3A09901 mov r9, #flash_protected ; Protect self from erase/write 966 0000101C E3A0A302 mov r10, #ROM_base ; Point at flash memory 967 00001020 E51FB020 ldr r11, Prog_host_link ; Pointer to UART 968 00001024 969 00001024 GET fp1.s ; Main body of code 1 00001024 ;------------------------------------------------------- ----------------------- 2 00001024 ; Manchester University ARM/Xilinx board software 3 00001024 ; Flash ROM programming code 4 00001024 ; 5 00001024 ; J. Garside November 2001 6 00001024 7 00001024 ; To do: 8 00001024 ; Locking 9 00001024 10 00001024 11 00001024 ; Do not corrupt: 12 00001024 ; R9 contains lowest modifiable address 13 00001024 ; R10 contains base address (if needed) 14 00001024 ; R11 contains pointer to UART ARM Macro Assembler Page 49 15 00001024 16 00001024 00200000 flash_size EQU &00200000 ; 2 Mbytes 17 00001024 00004000 flash_protected EQU &00004000 ; 16 Kbytes - can't modify o wn ROM 18 00001024 ; Protects up to boot_table 19 00001024 20 00001024 00000800 Flash_load_buffer EQU &800 ; Safely above code if in RA M 21 00001024 00000010 Flash_comm_buff_len EQU 16 ; NB Reserve 18 bytes 22 00001024 23 00001024 02000000 Erase_timeout EQU &02000000 ; About 6s if ALL at 40MHz 24 00001024 00000120 Write_timeout EQU &120 ; 50us if ALL at 40MHz 25 00001024 26 00001024 27 00001024 FEA51B1E Flash_Challenge EQU &FEA51B1E ; 28 00001024 FEE1900D Flash_Response EQU &FEE1900D ; 29 00001024 30 00001024 ;------------------------------------------------------- ----------------------- 31 00001024 32 00001024 33 00001024 EB0000F3 Flash_check bl Prog_Host_in ; Get first byte 34 00001028 E35000FE cmp r0, #(Flash_Challenge :SHR: 24) :AND: &F F 35 0000102C 1AFFFFFC bne Flash_check ; Fail, keep listening 36 00001030 EB0000F0 bl Prog_Host_in ; Get second byte 37 00001034 E35000A5 cmp r0, #(Flash_Challenge :SHR: 16) :AND: &F F 38 00001038 1AFFFFF9 bne Flash_check ; 39 0000103C EB0000ED bl Prog_Host_in ; etc. 40 00001040 E350001B cmp r0, #(Flash_Challenge :SHR: 8) :AND: &FF 41 00001044 1AFFFFF6 bne Flash_check ; 42 00001048 EB0000EA bl Prog_Host_in ; 43 0000104C E350001E cmp r0, #Flash_Challenge :AND: &FF 44 00001050 1AFFFFF3 bne Flash_check ; 45 00001054 46 00001054 E3A000FE mov r0, #(Flash_Response :SHR: 24) :AND: &FF 47 00001058 EB0000E0 bl Prog_Host_out ; Send reply ... 48 0000105C E3A000E1 mov r0, #(Flash_Response :SHR: 16) :AND: &FF 49 00001060 EB0000DE bl Prog_Host_out ; 50 00001064 E3A00090 mov r0, #(Flash_Response :SHR: 8) :AND: &FF ARM Macro Assembler Page 50 51 00001068 EB0000DC bl Prog_Host_out ; 52 0000106C E3A0000D mov r0, #Flash_Response :AND: &FF 53 00001070 EB0000DA bl Prog_Host_out ; 54 00001074 55 00001074 56 00001074 EB0000DF prog_loop bl Prog_Host_in ; Get command 57 00001078 58 00001078 E200007F and r0, r0, #&7F ; Clumsy dispatcher! 59 0000107C E3500052 cmp r0, #"R" ; 60 00001080 0A00000D beq prog_read ; 61 00001084 E3500057 cmp r0, #"W" ; 62 00001088 0A00001E beq prog_write ; (Programme) 63 0000108C E3500045 cmp r0, #"E" ; 64 00001090 0A00005D beq prog_erase ; 65 00001094 E3500050 cmp r0, #"P" ; 66 00001098 0A000083 beq prog_ping ; 67 0000109C E350004C cmp r0, #"L" ; 68 000010A0 0A000084 beq prog_lockout ; 69 000010A4 E3500043 cmp r0, #"C" ; 70 000010A8 0A000084 beq prog_check_lock ; 71 000010AC E3500049 cmp r0, #"I" ; 72 000010B0 0A00008C beq prog_dev_ID ; 73 000010B4 ; Else not recognised 74 000010B4 EB0000C9 bl Prog_Host_out ; Echo character 75 000010B8 EAFFFFED b prog_loop ; 76 000010BC 77 000010BC ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 78 000010BC 79 000010BC EB000090 prog_read bl Prog_Host_get_word ; 80 000010C0 E1A01000 mov r1, r0 ; Address 81 000010C4 EB00008E bl Prog_Host_get_word ; 82 000010C8 E1B02000 movs r2, r0 ; Length 83 000010CC 0A00000B beq prog_read_out ; Quit if zero bytes 84 000010D0 85 000010D0 E3A03010 prog_read_1 mov r3, #Flash_comm_buff_len ; 86 000010D4 87 000010D4 EB0000D4 prog_read_2 bl flash_r_byte ; Get byte 88 000010D8 E2811001 add r1, r1, #1 ; Increment address 89 000010DC EB0000BF bl Prog_Host_out ; Send character 90 000010E0 91 000010E0 E2522001 subs r2, r2, #1 ; Overall count 92 000010E4 0A000005 beq prog_read_out ; All done - exit 93 000010E8 E2533001 subs r3, r3, #1 ; Count on this `line' 94 000010EC 8AFFFFF8 bhi prog_read_2 ; Repeat <= "Flash_comm_buff _len" 95 000010F0 ; times 96 000010F0 EB0000C0 bl Prog_Host_in ; Then await an "A" 97 000010F4 E3500041 cmp r0, #"A" ; 98 000010F8 0AFFFFF4 beq prog_read_1 ; Another buffer load 99 000010FC EAFFFFDC b prog_loop ; or give up! ARM Macro Assembler Page 51 100 00001100 101 00001100 EB0000BC prog_read_out bl Prog_Host_in ; Then await an "A" (etc.) 102 00001104 EAFFFFDA b prog_loop ; 103 00001108 104 00001108 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 105 00001108 ; Write a sequence to the Flash 106 00001108 ; No real verification included 107 00001108 108 00001108 EB00007D prog_write bl Prog_Host_get_word ; Programme flash 109 0000110C E1A01000 mov r1, r0 ; Address 110 00001110 EB00007B bl Prog_Host_get_word ; 111 00001114 E1B02000 movs r2, r0 ; Length 112 00001118 0A000030 beq prog_write_out ; Quit if zero bytes 113 0000111C 114 0000111C E3A0004E mov r0, #"N" ; Not a real acknowledge 115 00001120 E1510009 cmp r1, r9 ; Protected area at bottom 116 00001124 3A000030 blo prog_write_error ; 117 00001128 E0813002 add r3, r1, r2 ; Find last address 118 0000112C E3530602 cmp r3, #flash_size ; 2Mbyte flash size 119 00001130 8A00002D bhi prog_write_error ; 120 00001134 121 00001134 E1A06001 mov r6, r1 ; Copy of address (in case o dd) 122 00001138 E3160001 tst r6, #1 ; Odd address? 123 0000113C 0A000003 beq prog_write_1 ; no 124 00001140 125 00001140 E3C11001 bic r1, r1, #1 ; Deal with odd start addres s 126 00001144 E3A04B02 mov r4, #Flash_load_buffer ; Temp. buffer space 127 00001148 EB0000B7 bl flash_r_byte ; Read previous address [R1] 128 0000114C E5C40000 strb r0, [r4] ; into first buffer locatio n 129 00001150 130 00001150 131 00001150 E3A04B02 prog_write_1 mov r4, #Flash_load_buffer ; Temp. buffer space 132 00001154 E3A03010 mov r3, #Flash_comm_buff_len ; 133 00001158 134 00001158 E3160001 tst r6, #1 ; Odd address? 135 0000115C 12844001 addne r4, r4, #1 ; yes - start one place in 136 00001160 137 00001160 EB0000A4 prog_write_2 bl Prog_Host_in ; Get byte 138 00001164 E4C40001 strb r0, [r4], #1 ; Save byte 139 00001168 140 00001168 E2522001 subs r2, r2, #1 ; Total count 141 0000116C 0A00000E beq prog_write_tidy ; Got last one ARM Macro Assembler Page 52 142 00001170 E2533001 subs r3, r3, #1 ; Line count 143 00001174 8AFFFFF9 bhi prog_write_2 ; Repeat <= through buffer 144 00001178 145 00001178 E3A04B02 mov r4, #Flash_load_buffer ; Temp. buffer space 146 0000117C E3A03008 mov r3, #Flash_comm_buff_len/2 ; Now in half words 147 00001180 148 00001180 E0D400B2 prog_write_3 ldrh r0, [r4], #2 ; 149 00001184 EB000068 bl flash_write ; No verification yet @@@ 150 00001188 151 00001188 E2811002 add r1, r1, #2 ; Destination address 152 0000118C E2533001 subs r3, r3, #1 ; 153 00001190 8AFFFFFA bhi prog_write_3 ; Buffer output loop 154 00001194 155 00001194 E3160001 tst r6, #1 ; Odd start address? 156 00001198 15D40000 ldrneb r0, [r4] ; then move last byte to st art 157 0000119C 15440010 strneb r0, [r4, #-Flash_comm_buff_len] 158 000011A0 ; Next pass must get this one 159 000011A0 160 000011A0 E3A00041 mov r0, #"A" ; 161 000011A4 EB00008D bl Prog_Host_out ; Send Acknowledge 162 000011A8 EAFFFFE8 b prog_write_1 ; and repeat 163 000011AC 164 000011AC E2443B02 prog_write_tidy sub r3, r4, #Flash_load_buffer ; Count remaindered bytes 165 000011B0 E3130001 tst r3, #1 ; Odd end address 166 000011B4 13A000FF movne r0, #&FF ; if so, pad with FF 167 000011B8 15C40000 strneb r0, [r4] ; (Does no damage & not test ed for) 168 000011BC 12833001 addne r3, r3, #1 ; 169 000011C0 170 000011C0 E1B030A3 movs r3, r3, lsr #1 ; Now in half words 171 000011C4 0A000005 beq prog_write_out ; None extra 172 000011C8 173 000011C8 E3A04B02 mov r4, #Flash_load_buffer ; Temp. buffer space 174 000011CC 175 000011CC E0D400B2 prog_write_4 ldrh r0, [r4], #2 ; 176 000011D0 EB000055 bl flash_write ; No verification yet @@@ 177 000011D4 178 000011D4 E2811002 add r1, r1, #2 ; Destination address 179 000011D8 E2533001 subs r3, r3, #1 ; 180 000011DC 8AFFFFFA bhi prog_write_4 ; Buffer output loop (II) 181 000011E0 182 000011E0 E3A00041 prog_write_out mov r0, #"A" ; 183 000011E4 EB00007D bl Prog_Host_out ; Send Acknowledge 184 000011E8 EAFFFFA1 b prog_loop ; and relax! 185 000011EC 186 000011EC prog_write_error ARM Macro Assembler Page 53 187 000011EC E3520010 cmp r2, #Flash_comm_buff_len ; Must be at least one byte 188 000011F0 83A02010 movhi r2, #Flash_comm_buff_len ; Only accept one `line' 189 000011F4 190 000011F4 prog_write_error1 191 000011F4 EB00007F bl Prog_Host_in ; Get byte 192 000011F8 E2522001 subs r2, r2, #1 ; 193 000011FC 8AFFFFFC bhi prog_write_error1 ; Repeat for `line' 194 00001200 195 00001200 E3A0004E mov r0, #"N" ; 196 00001204 EB000075 bl Prog_Host_out ; Send Non-acknowledge 197 00001208 EAFFFF99 b prog_loop ; and relax! 198 0000120C 199 0000120C ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 200 0000120C ; Erase block 201 0000120C ; Does not check block for blank; 202 0000120C ; such would need table of block sizes for different de vices. 203 0000120C 204 0000120C EB00003C prog_erase bl Prog_Host_get_word ; 205 00001210 E1A02000 mov r2, r0 ; Address into R2 206 00001214 207 00001214 E3A0004E mov r0, #"N" ; Not a real acknowledge 208 00001218 E1520009 cmp r2, r9 ; Protected area 209 0000121C 3A000020 blo prog_erase_error ; 210 00001220 E3520602 cmp r2, #flash_size ; 2Mbyte flash size 211 00001224 2A00001E bhs prog_erase_error ; Address too big 212 00001228 213 00001228 E3A000AA mov r0, #&AA ; Data #1 214 0000122C E3A01055 mov r1, #&55 ; Address 215 00001230 E3811C55 orr r1, r1, #&5500 ; 216 00001234 E1A01081 mov r1, r1, lsl #1 ; Flash A0 is our A1 217 00001238 EB000079 bl flash_w_hword ; 218 0000123C 219 0000123C E3A00055 mov r0, #&55 ; Data #2 220 00001240 E3A010AA mov r1, #&AA ; Address 221 00001244 E3811C2A orr r1, r1, #&2A00 ; 222 00001248 E1A01081 mov r1, r1, lsl #1 ; Flash A0 is our A1 223 0000124C EB000074 bl flash_w_hword ; 224 00001250 225 00001250 E3A00080 mov r0, #&80 ; Data #3 226 00001254 E3A01055 mov r1, #&55 ; Address 227 00001258 E3811C55 orr r1, r1, #&5500 ; 228 0000125C E1A01081 mov r1, r1, lsl #1 ; Flash A0 is our A1 229 00001260 EB00006F bl flash_w_hword ; 230 00001264 231 00001264 E3A000AA mov r0, #&AA ; Data #4 232 00001268 EB00006D bl flash_w_hword ; 233 0000126C 234 0000126C E3A00055 mov r0, #&55 ; Data #5 235 00001270 E3A010AA mov r1, #&AA ; Address 236 00001274 E3811C2A orr r1, r1, #&2A00 ; 237 00001278 E1A01081 mov r1, r1, lsl #1 ; Flash A0 is our A1 238 0000127C EB000068 bl flash_w_hword ; 239 00001280 ARM Macro Assembler Page 54 240 00001280 E1A01002 mov r1, r2 ; Restore address to R1 241 00001284 E3A00030 mov r0, #&30 ; Data #6 242 00001288 EB000065 bl flash_w_hword ; 243 0000128C 244 0000128C E3A000FF mov r0, #&FF ; Expected value 245 00001290 E3A05402 mov r5, #Erase_timeout ; 246 00001294 EB00005D bl flash_wtr ; Could check R5 for timeout 247 00001298 248 00001298 E1150005 tst r5, r5 ; 249 0000129C 03A0004E moveq R0, #"N" ; Timeout indicated 250 000012A0 13A00041 movne r0, #"A" ; Acknowledge if no timeout 251 000012A4 252 000012A4 prog_erase_error 253 000012A4 EB00004D bl Prog_Host_out ; Timeout is not, necessar ily 254 000012A8 EAFFFF71 b prog_loop ; the only fault. 255 000012AC 256 000012AC ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 257 000012AC 258 000012AC E3A00041 prog_ping mov r0, #"A" ; Just Acknowledge 259 000012B0 EB00004A bl Prog_Host_out ; 260 000012B4 EAFFFF6E b prog_loop ; 261 000012B8 262 000012B8 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 263 000012B8 264 000012B8 prog_lockout ; Nothing for now @@@ 265 000012B8 EB000048 bl Prog_Host_out ; Echo character @@@ 266 000012BC EAFFFF6C b prog_loop ; 267 000012C0 268 000012C0 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 269 000012C0 270 000012C0 EB00000F prog_check_lock bl Prog_Host_get_word ; 271 000012C4 E3C010FF bic r1, r0, #&FF ; Address 272 000012C8 E3C11C1F bic r1, r1, #&1F00 ; Clear (most) lower bits 273 000012CC E3811004 orr r1, r1, #4 ; Lockout check 274 000012D0 EB00002B bl flash_ID ; 275 000012D4 E3100001 tst r0, #1 ; 276 000012D8 03A0004E moveq r0, #"N" ; Not locked 277 000012DC 13A0004C movne r0, #"L" ; Locked 278 000012E0 EB00003E bl Prog_Host_out ; 279 000012E4 EAFFFF62 b prog_loop ; 280 000012E8 281 000012E8 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 282 000012E8 283 000012E8 E3A01000 prog_dev_ID mov r1, #0 ; Manufacturer code 284 000012EC EB000024 bl flash_ID ; 285 000012F0 EB00003A bl Prog_Host_out ; ARM Macro Assembler Page 55 286 000012F4 287 000012F4 E3A01002 mov r1, #2 ; Part code 288 000012F8 EB000021 bl flash_ID ; 289 000012FC EB000037 bl Prog_Host_out ; 290 00001300 291 00001300 EAFFFF5B b prog_loop ; 292 00001304 293 00001304 ;------------------------------------------------------- ----------------------- 294 00001304 295 00001304 Prog_Host_get_word 296 00001304 E92D4002 stmfd sp!, {r1,lr} ; 297 00001308 EB00003A bl Prog_Host_in ; 298 0000130C E1A01000 mov r1, r0 ; 299 00001310 EB000038 bl Prog_Host_in ; 300 00001314 E1811400 orr r1, r1, r0, lsl #8 ; 301 00001318 EB000036 bl Prog_Host_in ; 302 0000131C E1811800 orr r1, r1, r0, lsl #16 ; 303 00001320 EB000034 bl Prog_Host_in ; 304 00001324 E1810C00 orr r0, r1, r0, lsl #24 ; 305 00001328 E8BD8002 ldmfd sp!, {r1,pc} ; 306 0000132C 307 0000132C ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 308 0000132C ; Remote flash memory write routine 309 0000132C ; Halfword data in R0, address in R1 310 0000132C ; On exit R5 = 0 indicates timeout; R5 <> 0 indicates (p robably) okay 311 0000132C 312 0000132C E92D400F flash_write stmfd sp!, {r0-r3, lr} ; 313 00001330 314 00001330 E3A000AA mov r0, #&AA ; Data #1 315 00001334 E3A01055 mov r1, #&55 ; Address 316 00001338 E3811C55 orr r1, r1, #&5500 ; 317 0000133C E1A01081 mov r1, r1, lsl #1 ; Flash A0 is our A1 318 00001340 EB000037 bl flash_w_hword ; 319 00001344 320 00001344 E3A00055 mov r0, #&55 ; Data #2 321 00001348 E3A010AA mov r1, #&AA ; Address 322 0000134C E3811C2A orr r1, r1, #&2A00 ; 323 00001350 E1A01081 mov r1, r1, lsl #1 ; Flash A0 is our A1 324 00001354 EB000032 bl flash_w_hword ; 325 00001358 326 00001358 E3A000A0 mov r0, #&A0 ; Data #3 327 0000135C E3A01055 mov r1, #&55 ; Address 328 00001360 E3811C55 orr r1, r1, #&5500 ; 329 00001364 E1A01081 mov r1, r1, lsl #1 ; Flash A0 is our A1 330 00001368 EB00002D bl flash_w_hword ; 331 0000136C 332 0000136C E89D0003 ldmfd sp, {r0-r1} ; Restore data (NOT a pop) 333 00001370 EB00002B bl flash_w_hword ; 334 00001374 335 00001374 E20000FF and r0, r0, #&FF ; Just test one byte 336 00001378 E3A05E12 mov r5, #Write_timeout ; 337 0000137C EB000023 bl flash_wtr ; Wait for written (or timeo ut) 338 00001380 ARM Macro Assembler Page 56 339 00001380 E8BD800F ldmfd sp!, {r0-r3, pc} ; 340 00001384 341 00001384 ;; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 342 00001384 ;; Substitutes for monitor read routines to remote flash 343 00001384 ; 344 00001384 ;flash_read_w stmfd sp!, {r0, r2-r3, lr} ; 345 00001384 ; bic r2, r2, #3 ; Align anyway 346 00001384 ; mov r3, #0 ; Accumulator 347 00001384 ; mov r1, r2 ; Address 348 00001384 ;1 bl flash_r_byte ; Fetch R0 349 00001384 ; orr r3, r0, r3, ror #8 ; Data into acc. 350 00001384 ; add r1, r1, #1 ; Inc. address 351 00001384 ; tst r1, #3 ; Bottom addr. bits clear again? 352 00001384 ; bne %b1 ; no 353 00001384 ; mov r1, r3, ror #8 ; Realign for output 354 00001384 ; ldmfd sp!, {r0, r2-r3, pc} ; 355 00001384 ; 356 00001384 ;flash_read_b stmfd sp!, {r0, lr} ; 357 00001384 ; mov r1, r2 ; Address 358 00001384 ; bl flash_r_byte ; 359 00001384 ; mov r1, r0 ; Data 360 00001384 ; ldmfd sp!, {r0, pc} ; 361 00001384 362 00001384 ;------------------------------------------------------- ----------------------- 363 00001384 ; Read flash ID from address R1 into R0 364 00001384 ; 00000 = Manufacturer 365 00001384 ; 00002 = Part code 366 00001384 ; xx004 = Sector lockout state 367 00001384 368 00001384 E92D400E flash_ID stmfd sp!, {r1-r3, lr} ; 369 00001388 370 00001388 E3A000AA mov r0, #&AA ; Data #1 371 0000138C E3A01055 mov r1, #&55 ; Address 372 00001390 E3811C55 orr r1, r1, #&5500 ; 373 00001394 E1A01081 mov r1, r1, lsl #1 ; Flash A0 is our A1 374 00001398 EB000021 bl flash_w_hword ; 375 0000139C 376 0000139C E3A00055 mov r0, #&55 ; Data #2 377 000013A0 E3A010AA mov r1, #&AA ; Address 378 000013A4 E3811C2A orr r1, r1, #&2A00 ; 379 000013A8 E1A01081 mov r1, r1, lsl #1 ; Flash A0 is our A1 380 000013AC EB00001C bl flash_w_hword ; 381 000013B0 382 000013B0 E3A00090 mov r0, #&90 ; Data #3 383 000013B4 E3A01055 mov r1, #&55 ; Address 384 000013B8 E3811C55 orr r1, r1, #&5500 ; 385 000013BC E1A01081 mov r1, r1, lsl #1 ; Flash A0 is our A1 386 000013C0 EB000017 bl flash_w_hword ; 387 000013C4 388 000013C4 E89D0002 ldmfd sp, {r1} ; Restore R1 (address) 389 000013C8 390 000013C8 EB000017 bl flash_r_byte ; 391 000013CC E1A01000 mov r1, r0 ; Keep answer 392 000013D0 ARM Macro Assembler Page 57 393 000013D0 E3A000F0 mov r0, #&F0 ; Leave ID mode 394 000013D4 EB000012 bl flash_w_hword ; Address irrelevant 395 000013D8 396 000013D8 E1A00001 mov r0, r1 ; Reorganise registers 397 000013DC E8BD800E ldmfd sp!, {r1-r3, pc} ; 398 000013E0 399 000013E0 ;------------------------------------------------------- ----------------------- 400 000013E0 401 000013E0 END 970 000013E0 971 000013E0 ;------------------------------------------------------- ----------------------- 972 000013E0 ;------------------------------------------------------- ----------------------- 973 000013E0 ; Send character in R0 to serial line #0 974 000013E0 975 000013E0 E92D4004 Prog_Host_out stmfd sp!, {r2, lr} ; 976 000013E4 977 000013E4 E59B2014 Prog_Host_out1 ldr r2, [r11, #US_CSR] ; Pass byte to transm it in R0 978 000013E8 E3120002 tst r2, #TxRdy ; Test if ready to transmit 979 000013EC 0AFFFFFC beq Prog_Host_out1 ; 980 000013F0 981 000013F0 E58B001C Prog_Host_out2 str r0, [r11, #US_THR] ; Send character 982 000013F4 E8BD8004 ldmfd sp!, {r2, pc} ; 983 000013F8 984 000013F8 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 985 000013F8 ; Get character from serial line #0 into R0 986 000013F8 987 000013F8 E92D4000 Prog_Host_in stmfd sp!, {lr} ; 988 000013FC 989 000013FC E59B0014 Prog_Host_in1 ldr r0, [r11, #US_CSR] ; 990 00001400 E3100001 tst r0, #RxRdy ; Receiver ready? 991 00001404 0AFFFFFC beq Prog_Host_in1 ; 992 00001408 993 00001408 E59B0018 Prog_Host_in_rdy ldr r0, [r11, #US_RHR] ; Upper bits read as 0 994 0000140C E8BD8000 ldmfd sp!, {pc} ; Return byte in r0 995 00001410 996 00001410 ;------------------------------------------------------- ----------------------- 997 00001410 ; Device driving routines 998 00001410 ;------------------------------------------------------- ----------------------- 999 00001410 ; Wait for addressed location/R1 to contain R0 ARM Macro Assembler Page 58 1000 00001410 ; Timeout count in R5 1001 00001410 ; Returns R5 = 0 if timeout, else R5 <> 0 1002 00001410 ; Corrupts R2 1003 00001410 1004 00001410 E7DA2001 flash_wtr ldrb r2, [r10, r1] ; 1005 00001414 E2555001 subs r5, r5, #1 ; Decrement timeout 1006 00001418 11520000 cmpne r2, r0 ; 1007 0000141C 1AFFFFFB bne flash_wtr ; Wait for values to match 1008 00001420 1009 00001420 E1A0F00E mov pc, lr ; 1010 00001424 1011 00001424 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1012 00001424 1013 00001424 E18A00B1 flash_w_hword strh r0, [r10, r1] ; 1014 00001428 E1A0F00E mov pc, lr ; 1015 0000142C 1016 0000142C ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1017 0000142C ; Remote flash memory read routine 1018 0000142C ; Byte data into R0, address in R1 1019 0000142C 1020 0000142C E7DA0001 flash_r_byte ldrb r0, [r10, r1] ; 1021 00001430 E1A0F00E mov pc, lr ; 1022 00001434 1023 00001434 ;------------------------------------------------------- ----------------------- 1024 00001434 1025 00001434 ROM_loader_image_end ; End of RAM image 1026 00001434 1027 00001434 ;------------------------------------------------------- ----------------------- 1028 00001434 ;------------------------------------------------------- ----------------------- 1029 00001434 ; Default RAM image 1030 00001434 ; This version is simply an error trap/indicator 1031 00001434 ; 1032 00001434 ;RAM_image 1033 00001434 ; B Whoops ; Reset 1034 00001434 ; B Undefined ; Undefined 1035 00001434 ; B SWI ; SWI 1036 00001434 ; B Pabt ; Pabt 1037 00001434 ; B Dabt ; Dabt 1038 00001434 ; B Nothing ; Nothing! 1039 00001434 ; B IRQ ; IRQ 1040 00001434 ; B FIQ ; FIQ 1041 00001434 ; 1042 00001434 ;Whoops sub r0, r14, #4 ; Fault address 1043 00001434 ; bl Print_word ; 1044 00001434 ; mov r0, #&01 ; Identify fault 1045 00001434 ; b Error ; Park! 1046 00001434 ; 1047 00001434 ;Undefined sub r0, r14, #4 ; Fault address ARM Macro Assembler Page 59 1048 00001434 ; bl Print_word ; 1049 00001434 ; mov r0, #&02 ; Identify fault 1050 00001434 ; b Error ; Park! 1051 00001434 ; 1052 00001434 ;SWI sub r0, r14, #4 ; Fault address 1053 00001434 ; bl Print_word ; 1054 00001434 ; mov r0, #&04 ; Identify fault 1055 00001434 ; b Error ; Park! 1056 00001434 ; 1057 00001434 ;Pabt sub r0, r14, #4 ; Fault address 1058 00001434 ; bl Print_word ; 1059 00001434 ; mov r0, #&08 ; Identify fault 1060 00001434 ; b Error ; Park! 1061 00001434 ; 1062 00001434 ;Dabt sub r0, r14, #4 ; Fault address 1063 00001434 ; bl Print_word ; 1064 00001434 ; mov r0, #&10 ; Identify fault 1065 00001434 ; b Error ; Park! 1066 00001434 ; 1067 00001434 ;Nothing sub r0, r14, #4 ; Fault address 1068 00001434 ; bl Print_word ; 1069 00001434 ; mov r0, #&20 ; Identify fault 1070 00001434 ; b Error ; Park! 1071 00001434 ; 1072 00001434 ;IRQ sub r0, r14, #4 ; Fault address 1073 00001434 ; bl Print_word ; 1074 00001434 ; mov r0, #&40 ; Identify fault 1075 00001434 ; b Error ; Park! 1076 00001434 ; 1077 00001434 ;FIQ sub r0, r14, #4 ; Fault address 1078 00001434 ; bl Print_word ; 1079 00001434 ; mov r0, #&80 ; Identify fault 1080 00001434 ; b Error ; Park! 1081 00001434 ; 1082 00001434 ; 1083 00001434 ;Error mov r1, #(PIO_base :AND: byte3) 1084 00001434 ; orr r1, r1, #(PIO_base :AND: byte2) 1085 00001434 ; 1086 00001434 ; str r0, [r1,#PIO_CODR] 1087 00001434 ; str r0, [r1,#PIO_SODR] 1088 00001434 ; b Error 1089 00001434 ; 1090 00001434 ;;------------------------------------------------------ ------------------------ 1091 00001434 ;; Serial output of word in R0 - intended for RAMless op eration 1092 00001434 ;; Corrupts R1-R2, R13, R14 1093 00001434 ; 1094 00001434 ;Print_word mov r13, r14 ; Send a 32 bit value 1095 00001434 ; bl Put_byte ; `Stack' return address 1096 00001434 ; mov r0, r0, ror #8 ; 1097 00001434 ; bl Put_byte ; Shift by 8 each send 1098 00001434 ; mov r0, r0, ror #8 ; Repeat 4 times 1099 00001434 ; bl Put_byte ; 1100 00001434 ; mov r0, r0, ror #8 ; 1101 00001434 ; bl Put_byte ; 1102 00001434 ; mov r0, r0, ror #8 ; Restores R0 1103 00001434 ; mov pc, r13 ; Return 1104 00001434 ; ARM Macro Assembler Page 60 1105 00001434 ;; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1106 00001434 ;; Output R0 - corrupts R1, R2 1107 00001434 ; 1108 00001434 ;Put_byte ldr r1, RAM_US0_base ; 1109 00001434 ;Put_byte1 ldr r2, [r1, #US_CSR] ; Pass byte to transmit in R0 1110 00001434 ; tst r2, #TxRdy ; Test if ready to transmit 1111 00001434 ; beq Put_byte1 ; If not then loop 1112 00001434 ; str r0, [r1,#US_THR] ; 1113 00001434 ; mov pc, lr ; Return 1114 00001434 ; 1115 00001434 ;; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1116 00001434 ;; Input R0 - corrupts R1 1117 00001434 ; 1118 00001434 ;Get_byte ldr r1, RAM_US0_base ; 1119 00001434 ;Get_byte1 ldr r0, [r1, #US_CSR] ; Pass serial port base in r1 1120 00001434 ; tst r0, #RxRdy ; Test if byte received 1121 00001434 ; beq Get_byte1 ; If not then loop 1122 00001434 ; ldr r0, [r1,#US_RHR] 1123 00001434 ; mov pc, lr ; Return byte in r0 1124 00001434 ; 1125 00001434 ;; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1126 00001434 ; 1127 00001434 ;RAM_US0_base DCD US0_base ; 1128 00001434 ; 1129 00001434 ;; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1130 00001434 ; 1131 00001434 ;RAM_image_end 1132 00001434 ; 1133 00001434 ;------------------------------------------------------- ----------------------- 1134 00001434 1135 00001434 END