"; dot komodo file v 0.1.4-UNSW-1.5\n" "; [JNZ] Modified 27-Mar-2003\n" "\n" "; ARM v4, MIPS R3000 and STUMP (parts of 6809) instruction sets and\n" "; processor descriptions. You can always get the latest version from:\n" "; http://www.cs.man.ac.uk/teaching/electronics/komodo/.komodo. To learn\n" "; about Chump look at the description of STUMP at the bottom\n" "\n" "; This part of the file is for use only with KMD and is ignored by Chump\n" "; Chump parts starts from about line 100\n" "\n" "(\n" " (cpu 1 0 0 \"ARM\" ; CPU architecture-number max-verion min-version\n" " (memory-ptr-width 4) ; width of memory pointer (assumes 4)\n" " (wordalign 1) ; Are words word aligned?\n" " ; Too painful to explain.\n" " (window-list \"!~NCurrent.R0.User/System.R1.Supervisor.R2.Abort.R3.Undefined.R4.IRQ.R5.FIQ.R6||NCurrent Flags.F.Saved Flags.S~M~MC\")\n" " (regbanks 0 ; regbanks main-regbank\n" " (regbank-granularity 4) ; regbank minimum transfer\n" " (regbank \"Current\" 18 4 0 ; regbank \"name\" number-of-registers size-of-registers offset\n" " (names \"R0\" \"R1\" \"R2\" \"R3\" \"R4\" \"R5\" \"R6\" \"R7\"\n" " \"R8\" \"R9\" \"R10\" \"R11\" \"R12\" \"R13\" \"R14\" \"PC\" \"CPSR\" \"SPSR\")\n" " )\n" " (regbank \"User/System\" 17 4 32\n" " (names \"R0\" \"R1\" \"R2\" \"R3\" \"R4\" \"R5\" \"R6\" \"R7\"\n" " \"R8\" \"R9\" \"R10\" \"R11\" \"R12\" \"R13\" \"R14\" \"PC\" \"CPSR\" \"SPSR\")\n" " )\n" " (regbank \"Supervisor\" 18 4 64\n" " (names \"R0\" \"R1\" \"R2\" \"R3\" \"R4\" \"R5\" \"R6\" \"R7\"\n" " \"R8\" \"R9\" \"R10\" \"R11\" \"R12\" \"R13\" \"R14\" \"PC\" \"CPSR\" \"SPSR\")\n" " )\n" " (regbank \"Abort\" 18 4 96\n" " (names \"R0\" \"R1\" \"R2\" \"R3\" \"R4\" \"R5\" \"R6\" \"R7\"\n" " \"R8\" \"R9\" \"R10\" \"R11\" \"R12\" \"R13\" \"R14\" \"PC\" \"CPSR\" \"SPSR\")\n" " )\n" " (regbank \"Undefined\" 18 4 128\n" " (names \"R0\" \"R1\" \"R2\" \"R3\" \"R4\" \"R5\" \"R6\" \"R7\"\n" " \"R8\" \"R9\" \"R10\" \"R11\" \"R12\" \"R13\" \"R14\" \"PC\" \"CPSR\" \"SPSR\")\n" " )\n" " (regbank \"IRQ\" 18 4 160\n" " (names \"R0\" \"R1\" \"R2\" \"R3\" \"R4\" \"R5\" \"R6\" \"R7\"\n" " \"R8\" \"R9\" \"R10\" \"R11\" \"R12\" \"R13\" \"R14\" \"PC\" \"CPSR\" \"SPSR\")\n" " )\n" " (regbank \"FIQ\" 18 4 192\n" " (names \"R0\" \"R1\" \"R2\" \"R3\" \"R4\" \"R5\" \"R6\" \"R7\"\n" " \"R8\" \"R9\" \"R10\" \"R11\" \"R12\" \"R13\" \"R14\" \"PC\" \"CPSR\" \"SPSR\")\n" " ) \n" " (regbank \"Current Flags\" 4 0 540\n" " (names \"V\" \"C\" \"Z\" \"N\")\n" " )\n" " (regbank \"Saved Flags\" 4 0 572\n" " (names \"V\" \"C\" \"Z\" \"N\")\n" " )\n" " (regbank \"Pointers\" 16 4 0\n" " (names \"R0\" \"R1\" \"R2\" \"R3\" \"R4\" \"R5\" \"R6\" \"R7\"\n" " \"R8\" \"R9\" \"R10\" \"R11\" \"R12\" \"SP\" \"LR\" \"PC\")\n" " (pointers)\n" " (GREEN 15) ; associated to labels in the source\n" " (BLUE 14)\n" " (PURPLE 13)\n" " )\n" " )\n" " (isa \"ARM32\" ) ;removed MIPS32 STUMP16 later\n" " )\n" "\n" " (cpu 2 3000 0 \"MIPS\"\n" " (memory-ptr-width 4)\n" " (wordalign 1)\n" " (window-list \"~M!M|R0,|R1,R2\")\n" " (regbanks 0\n" " (regbank-granularity 4)\n" " (regbank \"CPU 0-15\" 16 4 0\n" " (names \"R0\" \"R1\" \"R2\" \"R3\" \"R4\" \"R5\" \"R6\" \"R7\"\n" " \"R8\" \"R9\" \"R10\" \"R11\" \"R12\" \"R13\" \"R14\" \"R15\"\n" " (pointers)\n" " )\n" " )\n" " (regbank \"CPU 16-31\" 16 4 16\n" " (names \"R16\" \"R17\" \"R18\" \"R19\" \"R20\" \"R21\" \"R22\" \"R23\"\n" " \"R24\" \"R25\" \"R26\" \"R27\" \"R28\" \"R29\" \"R30\" \"R31\"\n" " )\n" " (pointers)\n" " )\n" " (regbank \"CP0\" 15 4 32\n" " (names \"index\" \"rand\" \"E_lo\" \"con\"\n" " \"bvadr\" \"e_hi\" \"sr\" \"cause\"\n" " \"prid\" \"HI\" \"LO\" \"dreg\"\n" " \"dval\" \"NEXTPC\" \"PC\" )\n" " (pointers)\n" " (GREEN 14)\n" " (PURPLE 13)\n" " )\n" " )\n" " (isa \"MIPS32\")\n" " )\n" "\n" "; Now the Chump descriptions start\n" "\n" "; This is basically a list of pairs of elements, defined recursively.\n" "; The first element (LHS) is as ASCII string; the second element (RHS)\n" "; is a bitfield description. The bitfield is defined by letters {O, I,\n" "; Z, X} which mean {\"must be 0\", \"must be 1\" \"should be zero\", \"should\n" "; be 1\"} respectively. \"Should be\"s are defaults when assembling but\n" "; not insisted upon be the disassembler.\n" ";\n" "; The translation software assembles by matching a LHS and producing a\n" "; corresponding RHS, and disassembles with the reverse process. If\n" "; there is more than one possible match the first one in the list is\n" "; used. Special cases are therefore commonly defined before general\n" "; cases, so they are trapped out first.\n" ";\n" "; Alphabetics are case insensitive.\n" ";\n" "; Spaces are `whitespace' in assembler input and single spaces in\n" "; disassembler output.\n" ";\n" "; Tab (' ' takes a parameter which occupies the rest of that string\n" "; segment. For example \" f10\" means move forwards at least one space\n" "; to at least column 10. (CB was unsure -exactly- what this did at time\n" "; of writing.\n" ";\n" "; Futher descriptions are embedded in the code below as they are\n" "; encountered, marked **\n" "\n" "\n" " (isa \"ARM32\" ; ARM 32 instruction set\n" " (define \"reg\" ((\"R0\") (OOOO)) ; Registers\n" " ((\"R1\") (OOOI)) ; ** String \"R1\" is always 0001\n" " ((\"R2\") (OOIO))\n" " ((\"R3\") (OOII))\n" " ((\"R4\") (OIOO))\n" " ((\"R5\") (OIOI))\n" " ((\"R6\") (OIIO))\n" " ((\"R7\") (OIII))\n" " ((\"R8\") (IOOO))\n" " ((\"R9\") (IOOI))\n" " ((\"R10\") (IOIO))\n" " ((\"R11\") (IOII))\n" " ((\"R12\") (IIOO))\n" " ((\"R13\") (IIOI)) ; ** 1101 disassembles to R13\n" " ((\"SP\") (IIOI)) ; ** but SP also assembles to 1101\n" " ((\"R14\") (IIIO))\n" " ((\"LR\") (IIIO))\n" " ((\"PC\") (IIII)) ; R15 aliased with PC\n" " ((\"R15\") (IIII)))\n" "\n" " (define \"condition\" ((\"\") (IIIO)) ; Conditions\n" " ((\"EQ\") (OOOO))\n" " ((\"NE\") (OOOI))\n" " ((\"CS\") (OOIO))\n" " ((\"HS\") (OOIO))\n" " ((\"CC\") (OOII))\n" " ((\"LO\") (OOII))\n" " ((\"MI\") (OIOO))\n" " ((\"PL\") (OIOI))\n" " ((\"VS\") (OIIO))\n" " ((\"VC\") (OIII))\n" " ((\"HI\") (IOOO))\n" " ((\"LS\") (IOOI))\n" " ((\"GE\") (IOIO))\n" " ((\"LT\") (IOII))\n" " ((\"GT\") (IIOO))\n" " ((\"LE\") (IIOI))\n" " ((\"AL\") (IIIO)) ; AL aliased with \"\"\n" " ((\"NV\") (IIII)))\n" "\n" "\n" " (define \"tests\" ((\"TST\") (OO)) ; rn rm\n" " ((\"TEQ\") (OI)) ; rn rm\n" " ((\"CMP\") (IO)) ; rn rm\n" " ((\"CMN\") (II))) ; rn rm\n" "\n" " (define \"dataop\" ((\"AND\") (OOOO)) ; 3\n" " ((\"EOR\") (OOOI)) ; 3\n" " ((\"SUB\") (OOIO)) ; 3\n" " ((\"RSB\") (OOII)) ; 3\n" " ((\"ADD\") (OIOO)) ; 3\n" " ((\"ADC\") (OIOI)) ; 3\n" " ((\"SBC\") (OIIO)) ; 3\n" " ((\"RSC\") (OIII)) ; 3\n" " ((\"ORR\") (IIOO)) ; 3\n" " ((\"BIC\") (IIIO))) ; 3\n" "\n" " (define \"moves\" ((\"MOV\") (IIOI)) ; 2\n" " ((\"MVN\") (IIII))) ; 2\n" "\n" "\n" " (define \"shift\" ((\"LSL\") (OO)) ; Shift types\n" " ((\"LSR\") (OI))\n" " ((\"ASR\") (IO))\n" " ((\"ROR\") (II)))\n" " (define \"set\" ((\"S\") (I)) ; Set flags bit\n" " ((\"\") (O)))\n" " (define \"sign\" ((\"U\") (O)) ; Sign for multiplication\n" " ((\"S\") (I)))\n" "\n" " (define \"rd\" reg) ; **\"rd\" is substituted by any reg string\n" " (define \"rn\" reg)\n" " (define \"rm\" reg)\n" " (define \"rs\" reg)\n" " (define \"hex\" ((\"0x\")()) ((\"&\")()) (()()) )\n" "\n" " ; ARM rotated immediate fields\n" " (define \"rotimm\" (((\"imm\" (uint 8))) (OOOO imm)) ; **Straight 8-bit integer\n" " (((\"imm\" (uint 8 @32 2))) (OOOI imm)) ; **8-bit quantity ROR 2 places in 32-bit field\n" " (((\"imm\" (uint 8 @32 4))) (OOIO imm))\n" " (((\"imm\" (uint 8 @32 6))) (OOII imm))\n" " (((\"imm\" (uint 8 @32 8))) (OIOO imm))\n" " (((\"imm\" (uint 8 @32 10))) (OIOI imm))\n" " (((\"imm\" (uint 8 @32 12))) (OIIO imm))\n" " (((\"imm\" (uint 8 @32 14))) (OIII imm))\n" " (((\"imm\" (uint 8 @32 16))) (IOOO imm))\n" " (((\"imm\" (uint 8 @32 18))) (IOOI imm))\n" " (((\"imm\" (uint 8 @32 20))) (IOIO imm))\n" " (((\"imm\" (uint 8 @32 22))) (IOII imm))\n" " (((\"imm\" (uint 8 @32 24))) (IIOO imm))\n" " (((\"imm\" (uint 8 @32 26))) (IIOI imm))\n" " (((\"imm\" (uint 8 @32 28))) (IIIO imm))\n" " (((\"imm\" (uint 8 @32 30))) (IIII imm)))\n" "\n" "\n" "\n" " ((\"NOP\") (IIIOOOOI IOIOOOOO OOOOOOOO OOOOOOOO)) ; MOV R0, R0\n" " ((\"NOP\") (OOOOOOOO OOOOOOOO OOOOOOOO OOOOOOOO))\n" " ((\"MRS\" condition \" f10\" rd \", \" (\"psr\" ((\"CPSR\")(O)) ; e.g. MRS R0, CPSR\n" " ((\"SPSR\")(I)) ) )\n" " (condition OOOI O psr OO XXXX rd ZZZZ ZZZO ZZZZ))\n" "; ** unused bits {'Z', 'X'} ignored in disassembler but assemble correctly\n" "\n" "; ** In the preceding description the LHS comprises \"MRS\", a condition\n" "; string previously defined (including the possibility of \"\") space\n" "; which, during disassemble will tab. to column 10, rd - which is a\n" "; `register', a comma and finally one of the \"?PSR\" strings - which one\n" "; is tagged as `psr'. The RHS is the corresponding `condition' bitfield\n" "; (RHS), 0001, etc.\n" "\n" " ((\"MSR\" condition \" f10\" (\"psr\" ((\"CPSR\")(O)) ; e.g. MSR SPSR_flags, 90000000\n" " ((\"SPSR\")(I)) )\n" " (\"mask\"((\"_f\") (IOOO))\n" " ((\"_c\") (OOOI))\n" " ((\"_csxf\") (IIII))\n" " ((\"_all\") (IIII))\n" " ((\"_none?\") (OOOO))\n" " ((\"\") (IIII))\n" " ((\"_unknown\") (ZZZZ)))\n" " \", #\" hex rotimm)\n" " (condition OOII O psr IO mask ZZZZ rotimm hex)) ; ** \"hex\" on RHS is null string for `balance'\n" "\n" " ((\"MSR\" condition \" f10\" (\"psr\" ((\"CPSR\")(O)) ; e.g. MSR SPSR_flags, R1\n" " ((\"SPSR\")(I)) )\n" " (\"mask\"((\"_f\") (IOOO))\n" " ((\"_c\") (OOOI))\n" " ((\"_csxf\") (IIII))\n" " ((\"_all\") (IIII))\n" " ((\"_none?\") (OOOO))\n" " ((\"\") (IIII))\n" " ((\"_unknown\") (ZZZZ)))\n" " \", \" rm)\n" " (condition OOOI O psr IO mask XXXX ZZZZ ZZZO rm))\n" "\n" " ((\"CLZ\" condition \" f10\" rd \", \" rm)\n" " (condition OOOI OIIO XXXX rd XXXX OOOI rm))\n" "\n" " (define \"shiftop\" ((rm) (OOOOO OOO rm) )\n" " ((rm \", RRX\") (OOOOO IIO rm) ) ; replace ROR #0 with RRX\n" " ((rm \", LSR #0x20\") (OOOOO OIO rm) ) ; replace LSR #0 with LSR #32\n" " ((rm \", ASR #0x20\") (OOOOO IOO rm) ) ; replace ASR #0 with ASR #32\n" " ((rm\", \" shift \" #\" hex (\"imm\" (uint 5)))\n" " (imm shift O rm hex))\n" " ((rm\", \" shift \" \" rs)\n" " (rs O shift I rm)))\n" "\n" " ((tests condition \" f10\" rn \", #\" hex rotimm) ; 2 operand no destination ops\n" " (condition OOI IO tests I rn ZZZZ rotimm hex)) ; e.g. TST R2, #&12000\n" "\n" " ((tests condition \" f10\" rn \", \" shiftop) ; e.g. TST R2, R4, LSR #&1F\n" " (condition OOO IO tests I rn ZZZZ shiftop))\n" "\n" " ((moves condition set \" f10\" rd \", #\" hex rotimm)\n" " (condition OOI moves set ZZZZ rd rotimm hex)) ; e.g. MOV R4, #&1200\n" "\n" " ((moves condition set \" f10\" rd \", \" shiftop)\n" " (condition OOO moves set ZZZZ rd shiftop)) ; e.g. MOV R4, R7, ROR #&2\n" "\n" " ((dataop condition set \" f10\" rd ; e.g. ADD R4, R5, #&24000\n" " \", \" rn\n" " \", #\" hex rotimm)\n" " (condition OOI dataop set rn rd rotimm hex))\n" "\n" " ((dataop condition set \" f10\" rd ; e.g. SUB R4, R5, R4, ROR #&2\n" " \", \" rn\n" " \", \" shiftop )\n" " (condition OOO dataop set rn rd shiftop ))\n" "\n" "\n" " ((\"MUL\" condition set \" f10\" rn ; e.g. MUL R3, R2, R12\n" " \", \" rm\n" " \", \" rs)\n" " (condition OOO OOOO set rn ZZZZ rs IOOI rm ))\n" "\n" " ((\"MLA\" condition set \" f10\" rd ; e.g. MLA R3, R2, R12, R2\n" " \", \" rm\n" " \", \" rs\n" " \", \" rn)\n" " (condition OOO OOOI set rd rn rs IOOI rm ))\n" "\n" "\n" " ((sign (\"mul\" ((\"MULL\")(O)) ((\"MLAL\")(I))) ; e.g. SMULL R3, R2, R12, R2\n" " condition set \" f10\" rn\n" " \", \" rd\n" " \", \" rm\n" " \", \" rs)\n" " (condition OOOO I sign mul set rd rn rs IOOI rm ))\n" "\n" " ((\"BX\" condition \" f10\"rm)\n" " (condition OOOI OOIO ZZZZ ZZZZ ZZZZ OOOI rm )) ; e.g. BXEQ R12\n" "\n" "\n" " (define \"ldst\" ((\"STR\")(O)) ((\"LDR\")(I)))\n" " (define \"byte\" ((\"B\") (I)) ((\"\") (O)))\n" " (define \"sub\" ((\"-\") (O)) ((\"\") (I)))\n" " (define \"wb\" ((\"!\") (I)) ((\"\") (O)))\n" " (define \"tran\" ((\"T\") (I)) ((\"\") (O)))\n" "\n" "\n" "; [JNZ] We want a \"raw\" disassembler, so disable the following...\n" ";\n" "; ((ldst condition byte \" f10\" ; e.g. LDRB R3, &145\n" "; rd \", \" hex\n" "; (\"imm\" (urelative 12 - 8)) )\n" "; (condition OIOI I byte O ldst IIII rd imm hex))\n" ";\n" "; ((ldst condition byte \" f10\" ; e.g. LDRB R3, &145\n" "; rd \", \" hex\n" "; (\"imm\" (urelative 12 ~- 8)) )\n" "; (condition OIOI O byte O ldst IIII rd imm hex))\n" "\n" " ((ldst condition byte \" f10\" ; e.g. LDRB R3, [R2]\n" " rd \", [\"\n" " rn \"]\")\n" " (condition OIOI X byte Z ldst rn rd OOOO OOOO OOOO))\n" "\n" " ((ldst condition byte \" f10\" ; e.g. LDRB R3, [R2, #&123]!\n" " rd \", [\"\n" " rn \", #\" sub hex (\"imm\" (uint 12)) \"]\"\n" " wb)\n" " (condition OIOI sub byte wb ldst rn rd imm hex))\n" "\n" " ((ldst condition tran byte \" f10\" ; e.g. LDRB R3, [R2], #&123\n" " rd \", [\"\n" " rn \"], #\" sub hex (\"imm\" (uint 12)) )\n" " (condition OIOO sub byte tran ldst rn rd imm hex))\n" "\n" "\n" " ((ldst condition byte \" f10\" rd ; e.g. LDRB R3, [R2, -R3]\n" " \", [\" rn \", \" sub rm \"]\" wb)\n" " (condition OIII sub byte wb ldst rn rd OOOO OOOO rm))\n" "\n" " ((ldst condition tran byte \" f10\" rd \", [\" rn \"], \" sub rm ) ;e.g. LDRB R3, [R2], -R3\n" " (condition OIIO sub byte tran ldst rn rd OOOO OOOO rm))\n" "\n" "\n" " ((ldst condition byte \" f10\" ; e.g. STR R4, [R3, R7, ROR #&2]\n" " rd \", [\"\n" " rn \", \"\n" " sub rm \", \"\n" " shift \" #\" hex\n" " (\"imm\" (uint 5 / 2)) \"]\"\n" " wb)\n" " (condition OIII sub byte wb ldst rn rd imm shift O rm hex))\n" "\n" " ((ldst condition tran byte \" f10\" ; e.g. STR R4, [R3], R7, ROR #&2\n" " rd \", [\"\n" " rn \"], \"\n" " sub rm \", \"\n" " shift \" #\" hex\n" " (\"imm\" (uint 5 / 2)))\n" " (condition OIIO sub byte tran ldst rn rd imm shift O rm hex))\n" "\n" " ((\"SWP\" condition byte \" f10\" ; e.g. SWP R4, R2, [R4]\n" " rd \", \"\n" " rm \", [\"\n" " rn \"]\")\n" " (condition OOOI O byte ZZ rn rd ZZZZ IOOI rm))\n" "\n" " (define \"sh\" ((\"H\") (OI))\n" " ((\"SH\") (II))\n" " ((\"SB\") (XO)) )\n" "\n" " ((ldst condition sh \" f10\" ; e.g. LDRH R7, [R8, #&13]\n" " rd \", [\"\n" " rn \", #\" sub hex\n" " (\"immHi\" (uint 4)) ; This is a patch!!\n" " (\"immLo\" (uint 4)) \"]\" ; FIXME!!! assembly doesn't work\n" " wb)\n" " (condition OOOI sub I wb ldst rn rd immHi I sh I immLo hex))\n" "\n" " ((ldst condition sh \" f10\" ; e.g. LDRH R7, [R8], #&13\n" " rd \", [\"\n" " rn \"], #\" sub hex\n" " (\"immHi\" (uint 4)) ; This is a patch!!\n" " (\"immLo\" (uint 4)) ) ; FIXME!!! assembly doesn't work\n" "\n" " (condition OOOO sub IO ldst rn rd immHi I sh I immLo hex))\n" "\n" "\n" " ((ldst condition sh \" f10\" ; e.g. LDRH R7, [R8, -R4]\n" " rd \", [\"\n" " rn \", \"\n" " sub\n" " rm \"]\"\n" " wb)\n" " (condition OOOI sub O wb ldst rn rd ZZZZ I sh I rm) )\n" "\n" " ((ldst condition sh \" f10\" ; e.g. LDRH R7, [R8], -R4\n" " rd \", [\"\n" " rn \"], \"\n" " sub rm)\n" " (condition OOOO sub OI ldst rn rd ZZZZ I sh I rm))\n" "\n" " (define \"registerlist15\" ((\",PC\") (I)) ; LDM and STM instructions\n" " ((\",R15\")(I))\n" " (( ) (O)))\n" "\n" " (define \"registerlists15\" ((\"PC\") (I))\n" " ((\"R15\") (I))\n" " ((\"R14\") (O)) )\n" "\n" " (define \"registerlist14\" ((\", R14-PC\" )(II))\n" " ((\", R14-R15\")(II))\n" " ((\", R14\" ) (OI))\n" " ((registerlist15 ) (registerlist15 O)))\n" " (define \"registerlists14\"((\"R13\" registerlist15 ) (registerlist15 O))\n" " ((registerlists15) (registerlists15 I)) )\n" " (define \"registerlist13\" ((\", R13-\" registerlists15) (registerlists15 II))\n" " ((\", R13\" registerlist14 ) (registerlist14 I))\n" " ((registerlist14 ) (registerlist14 O)) )\n" " (define \"registerlists13\"((\"R12\" registerlist14 ) (registerlist14 O))\n" " ((registerlists14 ) (registerlists14 I)) )\n" " (define \"registerlist12\" ((\", R12-\" registerlists14) (registerlists14 II))\n" " ((\", R12\" registerlist13 ) (registerlist13 I))\n" " ((registerlist13 ) (registerlist13 O)) )\n" " (define \"registerlists12\"((\"R11\" registerlist13 ) (registerlist13 O))\n" " ((registerlists13 ) (registerlists13 I)) )\n" " (define \"registerlist11\" ((\", R11-\" registerlists13) (registerlists13 II))\n" " ((\", R11\" registerlist12 ) (registerlist12 I))\n" " ((registerlist12 ) (registerlist12 O)) )\n" " (define \"registerlists11\"((\"R10\" registerlist12 ) (registerlist12 O))\n" " ((registerlists12 ) (registerlists12 I)) )\n" " (define \"registerlist10\" ((\", R10-\" registerlists12) (registerlists12 II))\n" " ((\", R10\" registerlist11 ) (registerlist11 I))\n" " ((registerlist11 ) (registerlist11 O)) )\n" " (define \"registerlists10\"((\"R9\" registerlist11 ) (registerlist11 O))\n" " ((registerlists11 ) (registerlists11 I)) )\n" " (define \"registerlist9\" ((\", R9-\" registerlists11) (registerlists11 II))\n" " ((\", R9\" registerlist10 ) (registerlist10 I))\n" " ((registerlist10 ) (registerlist10 O)) )\n" " (define \"registerlists9\" ((\"R8\" registerlist10 ) (registerlist10 O))\n" " ((registerlists10 ) (registerlists10 I)) )\n" " (define \"registerlist8\" ((\", R8-\" registerlists10) (registerlists10 II))\n" " ((\", R8\" registerlist9 ) (registerlist9 I))\n" " ((registerlist9 ) (registerlist9 O)) )\n" " (define \"registerlists8\" ((\"R7\" registerlist9 ) (registerlist9 O))\n" " ((registerlists9 ) (registerlists9 I)) )\n" " (define \"registerlist7\" ((\", R7-\" registerlists9 ) (registerlists9 II))\n" " ((\", R7\"registerlist8 ) (registerlist8 I))\n" " ((registerlist8 ) (registerlist8 O)) )\n" " (define \"registerlists7\" ((\"R6\"registerlist8 ) (registerlist8 O))\n" " ((registerlists8 ) (registerlists8 I)) )\n" " (define \"registerlist6\" ((\", R6-\" registerlists8 ) (registerlists8 II))\n" " ((\", R6\"registerlist7 ) (registerlist7 I))\n" " ((registerlist7 ) (registerlist7 O)) )\n" " (define \"registerlists6\" ((\"R5\"registerlist7 ) (registerlist7 O))\n" " ((registerlists7 ) (registerlists7 I)) )\n" " (define \"registerlist5\" ((\", R5-\" registerlists7 ) (registerlists7 II))\n" " ((\", R5\" registerlist6 ) (registerlist6 I))\n" " ((registerlist6 ) (registerlist6 O)) )\n" " (define \"registerlists5\" ((\"R4\" registerlist6 ) (registerlist6 O))\n" " ((registerlists6 ) (registerlists6 I)) )\n" " (define \"registerlist4\" ((\", R4-\" registerlists6 ) (registerlists6 II))\n" " ((\", R4\" registerlist5 ) (registerlist5 I))\n" " ((registerlist5 ) (registerlist5 O)) )\n" " (define \"registerlists4\" ((\"R3\" registerlist5 ) (registerlist5 O))\n" " ((registerlists5 ) (registerlists5 I)) )\n" " (define \"registerlist3\" ((\", R3-\" registerlists5) (registerlists5 II))\n" " ((\", R3\" registerlist4 ) (registerlist4 I))\n" " ((registerlist4 ) (registerlist4 O)) )\n" " (define \"registerlists3\" ((\"R2\" registerlist4 ) (registerlist4 O))\n" " ((registerlists4 ) (registerlists4 I)) )\n" " (define \"registerlist2\" ((\", R2-\" registerlists4 ) (registerlists4 II))\n" " ((\", R2\" registerlist3 ) (registerlist3 I))\n" " ((registerlist3 ) (registerlist3 O)) )\n" " (define \"registerlists2\" ((\"R1\" registerlist3 ) (registerlist3 O))\n" " ((registerlists3 ) (registerlists3 I)) )\n" " (define \"registerlist1\" ((\", R1-\" registerlists3) (registerlists3 II))\n" " ((\", R1\" registerlist2 ) (registerlist2 I))\n" " ((registerlist2 ) (registerlist2 O)) )\n" " (define \"registerlist\" ((\"R0-\" registerlists2 ) (registerlists2 II))\n" " ((\"R1-\" registerlists3 ) (registerlists3 IIO))\n" " ((\"R2-\" registerlists4 ) (registerlists4 IIOO))\n" " ((\"R3-\" registerlists5 ) (registerlists5 I IOOO))\n" " ((\"R4-\" registerlists6 ) (registerlists6 II OOOO))\n" " ((\"R5-\" registerlists7 ) (registerlists7 IIO OOOO))\n" " ((\"R6-\" registerlists8 ) (registerlists8 IIOO OOOO))\n" " ((\"R7-\" registerlists9 ) (registerlists9 I IOOO OOOO))\n" " ((\"R8-\" registerlists10 ) (registerlists10 II OOOO OOOO))\n" " ((\"R9-\" registerlists11 ) (registerlists11 IIO OOOO OOOO))\n" " ((\"R10-\" registerlists12 ) (registerlists12 IIOO OOOO OOOO))\n" " ((\"R11-\" registerlists13 ) (registerlists13 I IOOO OOOO OOOO))\n" " ((\"R12-\" registerlists14 ) (registerlists14 II OOOO OOOO OOOO))\n" " ((\"R13-\" registerlists15 ) (registerlists15 IIO OOOO OOOO OOOO))\n" " ((\"R14-PC\") ( IIOO OOOO OOOO OOOO))\n" " ((\"R14-R15\") ( IIOO OOOO OOOO OOOO))\n" "\n" " ((\"R0\" registerlist1 ) (registerlist1 I))\n" " ((\"R1\" registerlist2 ) (registerlist2 IO))\n" " ((\"R2\" registerlist3 ) (registerlist3 IOO))\n" " ((\"R3\" registerlist4 ) (registerlist4 IOOO))\n" " ((\"R4\" registerlist5 ) (registerlist5 I OOOO))\n" " ((\"R5\" registerlist6 ) (registerlist6 IO OOOO))\n" " ((\"R6\" registerlist7 ) (registerlist7 IOO OOOO))\n" " ((\"R7\" registerlist8 ) (registerlist8 IOOO OOOO))\n" " ((\"R8\" registerlist9 ) (registerlist9 I OOOO OOOO))\n" " ((\"R9\" registerlist10 ) (registerlist10 IO OOOO OOOO))\n" " ((\"R10\" registerlist11 ) (registerlist11 IOO OOOO OOOO))\n" " ((\"R11\" registerlist12 ) (registerlist12 IOOO OOOO OOOO))\n" " ((\"R12\" registerlist13 ) (registerlist13 I OOOO OOOO OOOO))\n" " ((\"R13\" registerlist14 ) (registerlist14 IO OOOO OOOO OOOO))\n" " ((\"LR\" registerlist15 ) (registerlist15 IOO OOOO OOOO OOOO))\n" " ((\"R14\" registerlist15 ) (registerlist15 IOO OOOO OOOO OOOO))\n" " ((\"PC\") ( IOOO OOOO OOOO OOOO))\n" " ((\"R15\") ( IOOO OOOO OOOO OOOO))\n" " ((\"none?\") ( OOOO OOOO OOOO OOOO))\n" " ((\"\") ( OOOO OOOO OOOO OOOO)))\n" "\n" "\n" " (define \"ldst\" ((\"STM\")(O)) ((\"LDM\")(I)))\n" "\n" " ((ldst condition (\"u\" ((\"D\")(O)) ; e.g. LDMDA R3, {R2-R3, R5-R7, R10}\n" " ((\"I\")(I)) )\n" " (\"p\" ((\"A\")(O))\n" " ((\"B\")(I)) ) \" f10\"\n" " rn wb\n" " \", {\"registerlist\"}\"\n" " (\"s\" (( )(O))\n" " ((\"^\")(I)) ) )\n" " (condition IOO p u s wb ldst rn registerlist))\n" "\n" " (define \"ldstc\" ((\"STC\")(O)) ((\"LDC\")(I)))\n" " (define \"cocond\" ((\"2\")(IIII))\n" " condition )\n" " (define \"clong\" ((\"L\") (I))\n" " (() (O)) )\n" " (define \"cop\" ((\"P1\" (\"no\" (uint 4 + 10))) (no))\n" " ((\"P\" (\"no\" (uint 4))) (no)) )\n" "\n" " ((ldstc cocond clong \" f10\" ; e.g. STC P1, R3, [R3]\n" " cop \", \"\n" " rd \", [\"\n" " rn \"]\")\n" " (cocond IIOZ Z clong Z ldstc rn rd cop OOOO OOOO))\n" "\n" " ((ldstc cocond clong \" f10\" ; e.g. STC P1, R3, [R3, #&10]\n" " cop \", \"\n" " rd \", [\"\n" " rn \", #\" sub hex (\"imm\" (uint 8 / 4)) \"]\"\n" " wb)\n" " (cocond IIOI sub clong wb ldstc rn rd cop imm hex))\n" "\n" " ((ldstc cocond clong \" f10\" ; e.g. STC P1, R3, [R3], #&-10\n" " cop \", \"\n" " rd \", [\"\n" " rn \"], #\" sub hex (\"imm\" (uint 8 / 4)))\n" " (cocond IIOO sub clong I ldstc rn rd cop imm hex))\n" "\n" " (define \"mrccr\" ((\"MCR\")(O))\n" " ((\"MRC\")(I)) )\n" "\n" " ((mrccr cocond \" f10\" ; e.g. MCR P1, R3, R10, R12\n" " cop \", \"\n" " rd \", \"\n" " rn \", \"\n" " rm)\n" " (cocond IIIO ZZZ mrccr rn rd cop ZZZ I rm))\n" "\n" " ((\"B\" (\"link\" ((\"L\" )(I)) ; e.g. B &1232C0\n" " ((\"\")(O)) )\n" " condition \" f10\" hex\n" " (\"offset\" (relative 24 - 8 / 4)) )\n" " (condition IOI link offset hex))\n" "\n" " ((\"SWI\" condition \" f10\" (\"number\" (uint 24))) ; e.g. SWI 1232C0\n" " (condition IIII number))\n" " )\n" "\n" "\n" " (isa \"MIPS32\"\n" " (define \"regnum\"\n" " ((\"0\") (OOOOO)) ((\"1\") (OOOOI))\n" " ((\"2\") (OOOIO)) ((\"3\") (OOOII))\n" " ((\"4\") (OOIOO)) ((\"5\") (OOIOI))\n" " ((\"6\") (OOIIO)) ((\"7\") (OOIII))\n" " ((\"8\") (OIOOO)) ((\"9\") (OIOOI))\n" " ((\"10\") (OIOIO)) ((\"11\") (OIOII))\n" " ((\"12\") (OIIOO)) ((\"13\") (OIIOI))\n" " ((\"14\") (OIIIO)) ((\"15\") (OIIII))\n" " ((\"16\") (IOOOO)) ((\"17\") (IOOOI))\n" " ((\"18\") (IOOIO)) ((\"19\") (IOOII))\n" " ((\"20\") (IOIOO)) ((\"21\") (IOIOI))\n" " ((\"22\") (IOIIO)) ((\"23\") (IOIII))\n" " ((\"24\") (IIOOO)) ((\"25\") (IIOOI))\n" " ((\"26\") (IIOIO)) ((\"27\") (IIOII))\n" " ((\"28\") (IIIOO)) ((\"29\") (IIIOI))\n" " ((\"3O\") (IIIIO)) ((\"31\") (IIIII)))\n" "\n" " (define \"reg\" ((\"$\" regnum)(regnum)) ; Annoyingly there are more register naming convensions\n" " ((\"R\" regnum)(regnum))\n" " ((\"RA\" )(IIIII )))\n" "\n" " (define \"and-link\"\n" " ((\"AL\") (I))\n" " ((\"\") (O)) )\n" "\n" " (define \"unsigned\"\n" " ((\"U\") (I))\n" " ((\"\") (O)) )\n" "\n" " (define \"special\"\n" " ((\"MOVE\" \" f10\" (\"rd\" reg) \", \" (\"rs\" reg)) ;e.g. MOVE $4, $3\n" " (rs OOOOO rd ZZZZZ IOOOO X))\n" " ((\"NOP\") (ZZZZZ ZZZZZ OOOOO ZZZZZ ZOOZZZ)) ;e.g. NOP\n" " ((( \"op\" ; e.g. SLL $4, $3, 11\n" " ((\"SLL \") (OO))\n" " ((\"SRL \") (IO))\n" " ((\"SRA \") (II)) ) \" f10\"\n" " (\"rd\" reg) \", \" (\"rt\" reg) \", \" (\"sa\" (uint 5)))\n" " ( ZZZZZ rt rd sa OOOO op ) )\n" " ((( \"op\" ; e.g. SLLV $4, $3, $5\n" " ((\"SLLV \") (OO))\n" " ((\"SRLV \") (IO))\n" " ((\"SRAV \") (II)) ) \" f10\"\n" " (\"rd\" reg) \", \" (\"rt\" reg) \", \" (\"rs\" reg))\n" " ( rs rt rd ZZZZZ OOOI op ) )\n" "\n" " ((( \"op\" ; e.g. ADD $4, $3, $5\n" " ((\"ADD\" unsigned \" \") (OOO unsigned))\n" " ((\"SUB\" unsigned \" \") (OOI unsigned))\n" " ((\"AND \") (OIOO))\n" " ((\"OR \") (OIOI))\n" " ((\"XOR \") (OIIO))\n" " ((\"NOR \") (OIII))\n" " ((\"SLT\" unsigned \" \") (IOI unsigned))) \" f10\"\n" " (\"rd\" reg) \", \" (\"rs\" reg) \", \" (\"rt\" reg))\n" " ( rs rt rd ZZZZZ IO op ) )\n" "\n" " ((\"JR \" \" f10\" reg ) (reg ZZZZZ ZZZZZ ZZZZZ OOIOOO) ) ;e.g. JR $31\n" " ((\"JALR \" \" f10\" (\"rs\" reg) \", \" (\"rd\" reg)) ;e.g. JALR $23, $31\n" " ( rs ZZZZZ rd ZZZZZ OOIOOI) )\n" "\n" " ((( \"op\" ; e.g. MUL $3, $2\n" " ((\"MUL\") (O))\n" " ((\"DIV\") (I))) unsigned \" f10\"\n" " (\"rs\" reg) \", \" (\"rt\" reg))\n" " ( rs rt ZZZZZ ZZZZZ OIIO op unsigned))\n" "\n" " ((\"MF\" ; e.g. MFHI $3\n" " ( \"mul-reg\"\n" " ((\"HI \") (O))\n" " ((\"LO \") (I))) \" f10\"\n" " reg ) ( ZZZZZ ZZZZZ reg ZZZZZ OIOO mul-reg O))\n" "\n" " ((\"MT\" ; e.g. MTLO $3\n" " ( \"mul-reg\"\n" " ((\"HI \") (O))\n" " ((\"LO \") (I))) \" f10\"\n" " reg) ( reg ZZZZZ ZZZZZ ZZZZZ OIOO mul-reg I))\n" "\n" " ((\"SYSCALL\") (ZZZZZ ZZZZZ ZZZZZ ZZZZZ OOIIOO)) ;e.g. SYSCALL\n" " ((\"BREAK\") (ZZZZZ ZZZZZ ZZZZZ ZZZZZ OOIIOI))) ;e.g. BREAK\n" "\n" " (define \"itype\" ((\"LI \" reg \", \"(\"imm\" (int 16))) (OOI OOOOO reg imm) ) ;e.g. LI $4, 123\n" " ((( \"op\" ;e.g. ORI $4, $2, 123\n" " ((\"ADDI\" unsigned \" \") (OO unsigned))\n" " ((\"SLTI\" unsigned \" \") (OI unsigned))\n" " ((\"ANDI \") (IOO))\n" " ((\"ORI \") (IOI))\n" " ((\"XORI \") (IIO))\n" " ((\"LUI \") (III)))\" f10\"\n" " (\"rt\" reg) \", \" (\"rs\" reg) \", \" (\"imm\" (int 16)))\n" " ( op rs rt imm) ) )\n" "\n" " (define \"ldst\" (( (\"dir\" ;e.g. LWC1 $4, 123($3)\n" " ((\"L\") (O))\n" " ((\"S\") (I)))\n" " \"WC\" (\"number\" (uint 2)) \" f10\" (\"rt\" reg) \", \"\n" " (\"offset\" (int 16)) \"(\" (\"base\" reg) \")\")\n" " (I dir O number base rt offset))\n" " (( (\"dir\"\n" " ((\"L\") (O))\n" " ((\"S\") (I)))\n" " ( \"size\" ;e.g. LWL $4, 123($3)\n" " ((\"B\" unsigned \" \") (unsigned OO))\n" " ((\"H\" unsigned \" \") (unsigned OI))\n" " ((\"W \") (OII))\n" " ((\"WL \") (OIO))\n" " ((\"WR \") (IIO)) )\" f10\"\n" " (\"rt\" reg)\", \" (\"offset\" (int 16))\n" " \"(\" (\"base\" reg) \")\")\n" " (O dir size base rt offset)) )\n" "\n" " (define \"coprocessor\" ((( \"move\" ;e.g. MFC0 $4, $2\n" " ((\"M\") (O))\n" " ((\"C\") (I)))\n" " ( \"dir\"\n" " ((\"F\") (O))\n" " ((\"T\") (I)))\n" " \"C\" (\"number\" (uint 2)) \" f10\"\n" " (\"rt\" reg) \", \" (\"rd\" reg))\n" " (OO number OO dir move O rt rd OOOOOOOOOOO))\n" " ((\"TLBR\") (OOOOIOOOOOOOOOOOOOOOOOOOOOOOOI))\n" " ((\"TLBWI\") (OOOOIOOOOOOOOOOOOOOOOOOOOOOOIO))\n" " ((\"TLBWR\") (OOOOIOOOOOOOOOOOOOOOOOOOOOOIIO))\n" " ((\"TLBP\") (OOOOIOOOOOOOOOOOOOOOOOOOOOIOOO))\n" " ((\"RFE\") (OOOOIOOOOOOOOOOOOOOOOOOOOIOOOO))\n" " ((\"COP\" (\"number\" (uint 2)) \" f10\" ;e.g. COP1 123\n" " (\"code\" (int 25)))\n" " (OO number I code))\n" " ((\"BC\" (\"number\" (uint 2)) ;e.g. BC1T 1000\n" " ( \"bool\" ((\"F \") (O))\n" " ((\"T \") (I))) \" f10\"\n" " (\"offset\" (relative 16 / 4 + 4)))\n" " (OO number OIOOO OOOO bool offset)) )\n" "\n" " (define \"brtype\" (define \"offset\" (relative 16 / 4 + 4 ))\n" " ((\"B\" and-link \" f10\" offset) ;e.g. B 30\n" " (OOIOOOOO and-link ZZZI offset))\n" " ((\"B\" ( \"cond\" ;e.g. BLEZ $3, 20\n" " ((\"LTZ\") (O))\n" " ((\"GEZ\") (I)))\n" " and-link \" f10\" reg \", \"offset)\n" " (OOI reg and-link ZZZ cond offset))\n" " ((\"B\" ( \"cond\" ;e.g. BEQ $3, $5, 20\n" " ((\"EQ \") (O))\n" " ((\"NE \") (I))) \" f10\"\n" " (\"rs\" reg) \", \" (\"rt\" reg) \", \" offset)\n" " (IO cond rs rt offset))\n" " ((\"B\" ( \"cond\" ;e.g. BLEZ $5, 20\n" " ((\"LEZ \") (O))\n" " ((\"GTZ \") (I))) \" f10\" reg \", \" offset )\n" " (II cond reg OOOOO offset)) )\n" "\n" "\n" "\n" " ((special) (OOOOOO special ))\n" " ((\"J\" and-link \" f10\" (\"ptr\" (int 26 / 4)))\n" " (OOOOI and-link ptr))\n" " ((brtype) (OOO brtype ))\n" " ((itype) (OOI itype ))\n" " ((coprocessor) (OI coprocessor ))\n" " ((ldst) (I ldst ))\n" " )\n" " (isa \"STUMP16\" ; STUMP is a simple 16-bit processor (C) Andrew Bardsley\n" " ; Use this description to learn chump\n" " ; This is not a good tutorial but you can get the basics\n" " ; Firstly the basics:\n" " ; The following is the correct syntax to describe a translation\n" " ; ((\"Disassembled descrption\")(Assembled description))\n" " ; disassembled description is simply a string or set of strings\n" " ; Assembled description is a set of bits I (always on),O (always off),\n" " ; X (don't care but set as on), Z (don't care but set as off)\n" " ; Be careful, I and O are LETTERS. The parser will complain if it doesn't understand.\n" " ; e.g. 1 : ((\"R3\")(OII)) - matches 011 to \"R3\"\n" " ; and \"R3\" to 011\n" " ; e.g. 2 : ((\"BR\")(OZX)) - matches 000, 001, 010 or 011 to \"BR\"\n" " ; and \"BR\" to 001\n" " ; e.g. 3 : ((\"PC\")(III))\n" " ; ((\"R7\")(III)) - matches 111, to \"PC\" as it's first in the list\n" " ; and \"PC\" or \"R7\" to 111\n" " ; e.g. 4 : (define \"set\" ((\"S\")(I)) defines a rule called \"set\"\n" " ; ((\"\") (O)) ) this rule can now be used in all rules below\n" " ; ((\"ADD\" set) (OI set)) we can now use the predefined rule in another rule\n" " ; remember to place the rule in both the binary and ASCII sections\n" " ; e.g. 5 : (define \"imm\" (int 4 + 4)) \"imm\" is defined to be a 4bit hex number. When DISASSEMBLING 4 is added\n" " ; e.g. 6 : (define \"imm\" (relative 4)) \"imm\" is defined to be a 4bit relative number offset from the current position\n" " ; e.g. 7 : ((\"#\" (\"imm\" (int 4))) (imm)) the imm rule is defined in the rule. It's only valid in this rule\n" " ; and previous definition is ignored in this rule\n" " ; Take a look at the STUMP instruction set\n" " ; Instruction types\n" " ; 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0\n" " ; 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0\n" " ; --------------------------------\n" " ; Type 1 OP |0|S| DST |SRCA |SRCB |SHIFT\n" " ; Type 2 OP |1|S| DST |SRCA | IMMEDIATE\n" " ; Cond Br 1|1|1|1| COND | OFFSET\n" "\n" "\n" "\n" " (define \"reg\" ((\"R0\")(OOO)) ((\"R1\")(OOI)) ; Firstly we 'define' a description of all the registers\n" " ((\"R2\")(OIO)) ((\"R3\")(OII)) ; R0 - 000, R1 - 001 ... PC - 111, R7 - 111\n" " ((\"R4\")(IOO)) ((\"R5\")(IOI)) ; 111 is overloaded, When disassembling it will choose the first\n" " ((\"R6\")(IIO)) ((\"PC\")(III)) ; one (\"PC\") but when assembling either is acceptable\n" " ((\"R7\")(III)))\n" " (define \"dst\" reg) ; DST is a register\n" " (define \"srca\" reg) ; so are SrcA and SrcB\n" " (define \"srcb\" reg)\n" " (define \"op\" ((\"ADD\")(OOO)) ((\"ADC\")(OOI)) ; These are the 6 OP codes\n" " ((\"SUB\")(OIO)) ((\"SBC\")(OII))\n" " ((\"AND\")(IOO)) ((\"OR\") (IOI)))\n" " (define \"set\" ((\"S\")(I)) ; If set bit is set then add an S onto the opcode\n" " ((\"\") (O))) ; e.g. ADD -> ADDS\n" "\n" " (define \"shift\" ((\"\") (OO)) ; Shift types\n" " ((\", ASR\") (OI))\n" " ((\", ROR\") (IO))\n" " ((\", RRC\") (II)))\n" "\n" " (define \"cond\" ((\"\") (OOOO)) ; Branch conditions\n" " ((\"AL\") (OOOO))\n" " ((\"NV\") (OOOI))\n" " ((\"HI\") (OOIO))\n" " ((\"LS\") (OOII))\n" " ((\"CC\") (OIOO))\n" " ((\"CS\") (OIOI))\n" " ((\"NE\") (OIIO))\n" " ((\"EQ\") (OIII))\n" " ((\"VC\") (IOOO))\n" " ((\"VS\") (IOOI))\n" " ((\"PL\") (IOIO))\n" " ((\"MI\") (IOII))\n" " ((\"GE\") (IIOO))\n" " ((\"LT\") (IIOI))\n" " ((\"GT\") (IIIO))\n" " ((\"LE\") (IIII)))\n" "\n" " (define \"dir\" ((\"LD\")(O)) ; The difference between an ST and an LD is in the S bit\n" " ((\"ST\")(I)))\n" "\n" "\n" " ((\"NOP\") (OZZ Z O OOO ZZZ ZZZ ZZ)) ; These are the descriptions of the instructions\n" " ((\"NOP\") (IOZ Z O OOO ZZZ ZZZ ZZ)) ; These two NOP descriptions overlap other instructions\n" "\n" " ((\"CMP\" \" f10\" srca \", \" srcb shift ) ; e.g. CMP R3, R6, ASR\n" " (OIO O I OOO srca srcb shift))\n" "\n" " ((\"CMP\" \" f10\" srca \", \" (\"imm\" (int 5)) ) ; e.g. CMP R4, 12\n" " (OIO I I OOO srca imm)) ; notice the inline definition if \"imm\"\n" "\n" " ((\"MOV\" set \" f10\" dst \", \" (\"imm\" (int 5))) ; e.g. MOVS R3, 12\n" " (OOOO set dst OOO imm))\n" "\n" " ((\"MOV\" set \" f10\" dst \", \" ( \"src\" ((reg)(OOO reg)) ; e.g. MOV R3, R5\n" " ((reg)(reg OOO))) shift) ; note inline definition can also be translations\n" " (OOOO set dst src shift))\n" "\n" "\n" " ((op set \" f10\" dst \", \" srca \", \" srcb shift) ; e.g. ADD R4, R7, R2\n" " (op O set dst srca srcb shift))\n" "\n" " ((op set \" f10\" dst \", \" srca \", \" (\"imm\" (int 5)) ) ; e.g. SUBS R6, R2, C\n" " (op I set dst srca imm))\n" "\n" " ((\"B\" cond \" f10\" (\"offset\" (relative 8 ))) ; e.g. BNE 100\n" " (IIII cond offset))\n" "\n" " ((dir \" f10\" dst \", [\" srca \", \" srcb shift \"]\") ; e.g. LD r4, [r3,r0]\n" " (IIO O dir dst srca srcb shift))\n" "\n" " ((dir \" f10\" dst \", [\" srca \", \" (\"imm\" (int 5)) \"]\") ; e.g. LD r4, [r3,12]\n" " (IIO I dir dst srca imm))\n" " )\n" "\n" " (isa \"MC6809\" ; This is just a little tester to see if chump copes with CISC ISAs\n" " (define \"aorb\" ((\"A\")(O))\n" " ((\"B\")(I)))\n" "\n" " (define \"abopps\"\n" " ((\"SUB\") (OOOO))\n" " ((\"CMP\") (OOOI))\n" " ((\"SBC\") (OOIO))\n" " ((\"AND\") (OIOO))\n" " ((\"BIT\") (OIOI))\n" " ((\"LD\") (OIIO))\n" " ((\"EOR\") (IOOO))\n" " ((\"ADC\") (IOOI))\n" " ((\"OR\") (IOIO))\n" " ((\"ADD\") (IOII)))\n" "\n" " (\n" " ((\"inherent\"\n" " ((\"ASR\")(OIII))\n" " ((\"ASL\")(IOOO))\n" " ((\"CLR\")(IIII))\n" " ((\"COM\")(OOII))\n" " ((\"DEC\")(IOIO))\n" " ((\"INC\")(IIOO))\n" " ((\"LSL\")(IOOO))\n" " ((\"LSR\")(OIOO))\n" " ((\"NEG\")(OOOO))\n" " ((\"ROL\")(IOOI))\n" " ((\"ROR\")(OIIO))\n" " ((\"TST\")(IIOI)))\n" " aorb) (OIO aorb inherent))\n" " ((\"RTI\") (OOIIIOII))\n" " ((\"RTS\") (OOIIIOOI))\n" " ((\"SEX\") (OOOIIIOI))\n" " ((\"SWI\") (OOIIIIII))\n" " ((\"SWI2\")(OOIIIIII OOOIOOOO ))\n" " ((\"SWI3\")(OOIIIIII OOOIOOOO ))\n" "\n" " ((abopps aorb \" f10\" \"#\" (\"imm\" (uint 8))) (imm I aorb OO abopps))\n" " ((abopps aorb \" f10\" \"<\" (\"imm\" (uint 16))) (imm I aorb II abopps))\n" "\n" "\n" " )\n" "\n" "\n" " (feature 0x11 0x0a01 \"xilinx-fpga\"\n" " (name \"Spartan XCS10XL\")\n" " (XFPGA-filestring \"s10xlvq100\")\n" " )\n" "\n" " (feature 0x12 0x1E02 \"xilinx-fpga\"\n" " (name \"Virtex XCV300\")\n" " (XFPGA-filestring \"v300pq240\")\n" " )\n" "\n" " (feature 0x13 0x1E02 \"xilinx-fpga\"\n" " (name \"Virtex-E XCV300E\")\n" " (XFPGA-filestring \"v300epq240\")\n" " )\n" "\n" " (feature 0x04 0x0005 \"added for redundancy\"\n" " (name \"ignore this feature, it does not exist\")\n" " )\n" "\n" " (feature 0x00 0xFFFF \"terminal\" ; FFFF meaning all.\n" " (name \"Terminal\")\n" " )\n" "\n" ")\n"